Time-Staggered Lockstep Memory Controller for Buffered DRAM
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Solution Overview
Problem
Dual channel lockstep memory controllers incur performance penalties due to data burst-length of 4, which is inefficient for newer DRAM devices like DDR3, and limits the use of chip-fail error correction codes in memory systems.
Innovation Solution
Implementing a DRAM sub-channel staggered lockstep configuration with time-staggered burst-length 4 commands to two DDR sub-channels behind a memory buffer, allowing for efficient data transfer akin to burst-length 8, while maintaining chip-fail ECC capabilities and reducing performance penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual channel lockstep configuration with burst-length 4 is used, then chip-fail ECC capabilities are enabled, but performance is degraded due to short data transfer duration compared to bus electrical turnarounds
Solution Approach 1:
The patent segments the burst-length 4 transfers into two separate half-burst transfers, allowing the first half to be transferred on one channel while the second half is transferred on the other channel. This segmentation enables longer effective transfer duration per channel while maintaining the lockstep error detection capability across both channels.
Solution Approach 2:
The patent implements periodic half-burst transfers alternated between two channels. Instead of completing a full burst-length 4 on one channel before switching, the system performs periodic half-burst transfers on channel 1, then channel 2, creating a staggered periodic pattern that extends the effective data transfer duration while maintaining electrical turnaround efficiency.
2Reliability
If burst-length 4 is used in dual channel lockstep mode, then data is distributed across twice as many DRAM devices for better error correction, but additional performance penalties occur with DDR3 devices optimized for burst-length 8
Solution Approach 1:
The patent segments the burst-length 4 operation into two burst-length 2 operations, with each half-burst transferred on a different channel. This allows DDR3 devices to operate in their optimized burst-length 8 mode while the memory controller presents an effective burst-length 4 to the system, maintaining both device optimization and error correction capability.
Solution Approach 2:
The patent adds a temporal dimension to the data transfer by staggering the half-burst transfers across time on different channels. Instead of parallel simultaneous transfers that force burst-length 4 constraints, the system uses time-staggered transfers that effectively create a longer transfer window, allowing DDR3 devices to operate in their native optimized mode.
Data Source
AI summary
Memory control techniques for dual channel lockstep configurations are disclosed. In accordance with one example embodiment, a memory controller issues two burst-length 4 DRAM commands to two double-data-rate (DDR) DRAM sub-channels behind a memory buffer (e.g., FB-DIMM or buffer-on-board). The two commands are in time-staggered lockstep. The time-stagger allows data coming back from the two back-side DDR sub-channels to flow naturally on the host channel without conflict. Multiple DIMMs can be used to obtain chip-fail ECC capabilities and to reclaim at least some of the lost performance imposed by the burst-length of 4 s typically associated with dual channel lockstep memory controllers. The techniques can be implemented, for instance, with a buffered memory solution such as fully buffered DIMM (FB-DIMM) or buffer-on-board configurations.