Staggered Memory Chip Drive Timing for Peak Current Control
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Solution Overview
Problem
In systems with multiple NAND type flash memory chips controlled by a single controller, the simultaneous operation of these chips can lead to peak current overlap, potentially causing power supply voltage drops and system malfunctions due to excessive current demand.
Innovation Solution
Implementing a controller that transmits drive instruction commands with a time interval of at least 5-10 μs to stagger the operational timing of memory chips, allowing them to ignore subsequent commands during peak current operations and reducing the need for status read commands, thereby preventing peak current overlap and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory chips are operated in parallel to improve system performance, then productivity is improved, but peak current concentration occurs causing power supply voltage drops and system malfunctions
Solution Approach 1:
The controller transmits drive instruction commands with a time interval of at least 5-10 μs between different memory chips, creating periodic staggered operation cycles. This timing-based periodic action distributes peak current demands across different time periods, preventing simultaneous current concentration while maintaining parallel operation benefits for system performance.
2Object-affected harmful factors
If drive instruction commands are transmitted with time intervals to stagger operations, then peak current overlap is reduced, but operation time increases
Solution Approach 1:
The controller transmits drive instruction commands to all memory chips but allows chips to ignore subsequent commands during peak current operations. This partial action approach sends commands to all chips (excessive) but only executes operations when safe (partial), preventing peak current overlap while minimizing idle time through efficient command utilization.
3Object-affected harmful factors
If memory chips ignore subsequent commands during operation execution, then peak current concentration is prevented, but command processing complexity increases
Solution Approach 1:
Each memory chip autonomously determines whether to execute or ignore drive instruction commands based on its own operational state. The chips self-manage their execution timing without requiring complex centralized coordination, reducing control logic complexity while effectively preventing peak current concentration through distributed self-service decision-making.
Data Source
AI summary
A semiconductor memory device of this embodiment comprises: a plurality of memory chips each including a plurality of memory cells; and a controller that controls the plurality of memory chips. The controller transmits to any of the plurality of memory chips a drive instruction command instructing an operation. The drive instruction command is transmitted sequentially to the plurality of memory chips with at least a first time interval. Each of the plurality of memory chips, when the memory chip itself is in a standby state of waiting for an instruction for one operation execution of an operation loop for a certain operation, starts the operation of the operation loop in response to the drive instruction command, while when the memory chip itself is in operation execution of the operation loop, ignores the drive instruction command.