Staggered Memory Die Initialization Circuit
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Solution Overview
Problem
Concurrent initialization of multiple memory dies in memory devices leads to power spikes, straining the power delivery network and causing interference with memory cells.
Innovation Solution
Introducing a delay in the initialization timing of individual memory dies, allowing them to initialize asynchronously rather than concurrently, by modifying the signaling timing associated with initialization and utilizing fuse arrays to program specific delay states for each memory die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple memory dies are initialized concurrently, then initialization speed is improved, but power spikes occur straining the power delivery network
Solution Approach 1:
The patent segments the concurrent initialization process into staggered phases by introducing delay circuits that divide the initialization sequence into multiple time slots. Each memory die is assigned a specific delay state (first, second, or third) that staggers their initialization timing, preventing simultaneous power requests and eliminating power spikes while maintaining efficient initialization throughput.
2Loss of time
If multiple memory dies are initialized concurrently, then initialization time is reduced, but supply voltage droop occurs causing interference with memory cells
Solution Approach 1:
The patent applies segmentation by dividing the initialization process into temporal segments using delay circuits. Memory dies are initialized in sequential batches rather than simultaneously, which segments the power demand over time. This prevents supply voltage droop that would occur with concurrent initialization, while the segmented approach completes initialization within the specified time frame without excessive delay.
3Power
If delay is introduced in initialization timing, then power spikes are reduced, but initialization time increases
Solution Approach 1:
The patent changes the timing parameter of initialization by introducing controllable delay circuits with multiple delay states. These circuits adjust the initialization timing parameter for each memory die independently, allowing the system to optimize the balance between power consumption and initialization time. The parameter change enables staggered initialization that reduces power spikes while maintaining acceptable initialization duration.
Data Source
AI summary
Signaling indicative of a command to initialize a plurality of memory dies of a memory device can be received by the memory device. Initialization of a memory die of the memory device can be delayed, at the memory die and based at least in part on fuse states of an array of fuses of the memory die, by an amount of time relative to receipt of the signaling by the memory device. Delaying initialization of memory dies of the memory device in a staggered or asynchronous manner can evenly distribute power consumption of the memory dies so that the likelihood of an associated power spike is reduced or eliminated.