Staggered Memory Module Data Transfer for Read Latency
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Solution Overview
Problem
Buffered memory modules introduce additional read latency, which negatively impacts processor wait times in computing systems that employ 'critical word first' policies.
Innovation Solution
Implementing a memory system architecture that staggers data transfers through finer data transfer granularity by partitioning memory modules into data threads, using buffer circuits to isolate memory devices from the primary data bus, and scheduling data bursts in a non-contiguous manner to minimize read latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If buffer circuitry is used to isolate memory devices from the primary data bus, then signal integrity is improved and parasitic loading is minimized, but read latency increases
Solution Approach 1:
The memory module is divided into multiple independent data threads (e.g., thread 0, thread 1, thread 2, thread 3), each capable of autonomous data transfer. This segmentation allows the memory controller to access different data threads in parallel, reducing the effective read latency by providing multiple concurrent data paths while maintaining the buffer isolation architecture.
Solution Approach 2:
The patent implements pipelined data transfer where multiple data threads are transferred in overlapping time periods. While one data thread is being transferred, another can be prepared or transferred simultaneously through different buffers, ensuring continuous useful action and minimizing idle time, thereby reducing overall read latency without compromising signal integrity.
2Productivity
If data transfers are performed in contiguous blocks, then data throughput is maximized, but processor wait time increases for critical word first policies
Solution Approach 1:
Data transfers are segmented into multiple independent data threads with finer granularity than traditional contiguous blocks. Each data thread can be transferred independently, allowing the processor to access critical words from one thread while other threads continue transferring, thus reducing processor wait time while maintaining high throughput through parallel transfers.
Solution Approach 2:
The patent enables partial data thread transfers where the processor can access available data from completed portions of data threads without waiting for the entire data block to be transferred. This partial action approach allows the processor to proceed with critical operations using available data while the remaining data continues to transfer in the background, reducing wait time without sacrificing overall throughput.
Data Source
AI summary
A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data thread across the primary data bus width is carried out over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval. During the first time interval, at least one data group from a second data thread is transferred on the primary data bus.