Staggered 3D Memory String Columns for Integration Density
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Solution Overview
Problem
Conventional 3D non-volatile memory devices face challenges in increasing integration density, packaging difficulties due to large page sizes, incompatibility with standard controllers, increased interference between memory cells, and limitations in reducing line width and tunnel insulating layer thickness, which hinder further integration and require new controller development.
Innovation Solution
A non-volatile memory device with a 3D structure featuring staggered string columns coupled to multiple bit lines, allowing for increased page size and reduced number of pages per memory block, achieved through the formation of U-shaped channels with interconnected drain and source-side memory cells and shared word lines, enabling efficient memory cell operation and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked vertically in 3D structure, then integration density is improved, but device complexity increases
Solution Approach 1:
The memory device is divided into multiple independent string columns, each containing a complete set of memory cells and select transistors. This segmentation allows the complex 3D structure to be managed as modular units, improving integration density while controlling complexity through standardized repeating blocks.
Solution Approach 2:
The patent transitions from 2D planar memory cells to 3D vertically-stacked memory cells arranged in multiple string columns. This dimensional change enables significantly higher integration density by utilizing the vertical dimension and multi-column arrangement, while the modular nature of each column helps manage the resulting device complexity.
2Quantity of substance
If page size is increased to improve integration density, then packaging difficulty increases
Solution Approach 1:
The memory device is divided into multiple independent string columns, each containing a complete set of memory cells and select transistors. This segmentation allows the complex 3D structure to be managed as modular units, improving integration density while controlling complexity through standardized repeating blocks.
Solution Approach 2:
The patent transitions from 2D planar memory cells to 3D vertically-stacked memory cells arranged in multiple string columns. This dimensional change enables significantly higher integration density by utilizing the vertical dimension and multi-column arrangement, while the modular nature of each column helps manage the resulting device complexity.
3Quantity of substance
If line width and tunnel insulating layer thickness are reduced to increase integration density, then manufacturing precision requirements increase
Solution Approach 1:
The memory device is divided into multiple independent string columns, each containing a complete set of memory cells and select transistors. This segmentation allows the complex 3D structure to be managed as modular units, improving integration density while controlling complexity through standardized repeating blocks.
Solution Approach 2:
The patent transitions from 2D planar memory cells to 3D vertically-stacked memory cells arranged in multiple string columns. This dimensional change enables significantly higher integration density by utilizing the vertical dimension and multi-column arrangement, while the modular nature of each column helps manage the resulting device complexity.
4Quantity of substance
If more memory cells are stacked vertically, then interference between memory cells increases
Solution Approach 1:
The memory device is divided into multiple independent string columns, each containing a complete set of memory cells and select transistors. This segmentation allows the complex 3D structure to be managed as modular units, improving integration density while controlling complexity through standardized repeating blocks.
Solution Approach 2:
The patent transitions from 2D planar memory cells to 3D vertically-stacked memory cells arranged in multiple string columns. This dimensional change enables significantly higher integration density by utilizing the vertical dimension and multi-column arrangement, while the modular nature of each column helps manage the resulting device complexity.
Data Source
AI summary
A non-volatile memory device comprising a plurality of strings each including a drain select transistor, drain-side memory cells, a pipe transistor, source-side memory cells, and a source select transistor coupled in series, wherein the plurality of strings are arranged in a first direction and a second direction, and the strings arranged in the second direction form each of string columns; a plurality of bit lines extended in the second direction and coupled to the drain select transistors of the strings included in each string column; and a plurality of source lines extended in the first direction and in common coupled to the source select transistors of strings adjacent to each other in the second direction, wherein strings included in one of the string columns are staggered in the first direction and each of the string columns are coupled to at least two of the bit lines.