Vertically-Staggered Metal Fill for Parasitic Capacitance

Solution Overview

Problem

Metal fill structures in semiconductor chips cause significant capacitive coupling, leading to slowed signal propagation due to their large conductive volume, which degrades the performance of semiconductor chips.

Innovation Solution

Implementing vertically-staggered-level metal fill structures with inner and outer metal fill groups separated by dielectric material, limiting each contiguous metal fill structure to no more than three vertically adjoining metal interconnect levels to minimize capacitive coupling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If metal fill structures are used to protect semiconductor structures, then protection against moisture or impurity ingress is improved, but capacitance increases due to large volume of conductive material

Engineering Contradiction:

Improveprotection against moisture or impurity ingressVSAvoidvolume of conductive material

Core Design Contradiction:

ReliabilityVSVolume of stationary object

Solution Approach 1:

The metal fill structure is divided into multiple discrete metal fill segments distributed across different dielectric layers rather than a single continuous structure. Each segment is separated by dielectric material, fragmenting the conductive volume while maintaining protective coverage throughout the semiconductor structure.

Inventive Principle:

Principle #1Segmentation

2Reliability

If metal fill structures are used to protect semiconductor structures, then protection against moisture or impurity ingress is improved, but signal propagation speed decreases due to capacitive coupling

Engineering Contradiction:

Improveprotection against moisture or impurity ingressVSAvoidsignal propagation speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The metal fill structure is divided into multiple discrete metal fill segments distributed across different dielectric layers rather than a single continuous structure. Each segment is separated by dielectric material, fragmenting the conductive volume while maintaining protective coverage throughout the semiconductor structure.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Metal fill segments are positioned at different vertical levels (different dielectric layers) creating a three-dimensional distributed arrangement. This vertical distribution reduces capacitive coupling between adjacent metal interconnect structures and the fill, as segments are separated both laterally and vertically.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Reliability

If contiguous metal fill structures extend from lowest to uppermost level, then protection coverage is maximized, but capacitance increases due to large conductive volume

Engineering Contradiction:

Improveprotection coverageVSAvoidconductive volume

Core Design Contradiction:

ReliabilityVSVolume of stationary object

Solution Approach 1:

The metal fill structure is divided into multiple discrete metal fill segments distributed across different dielectric layers rather than a single continuous structure. Each segment is separated by dielectric material, fragmenting the conductive volume while maintaining protective coverage throughout the semiconductor structure.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Multiple metal fill segments are nested across different dielectric layers, with each layer containing segments that collectively provide comprehensive protection. The segments at different levels work together to enclose and protect the semiconductor structures, creating a nested protective arrangement.

Inventive Principle:

Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces capacitive coupling between metal interconnect structures and metal fill structures, enhancing signal transmission speed and overall chip performance while maintaining effective protection against moisture and impurities.

Implementation Method 1

Capacitive coupling between metal interconnect structures and the metal fill structures may slow signal propagation in the metal interconnect structures

Methodology Applied

Scientific EffectCapacitive coupling: Capacitance

Implementation Method 2

A dielectric material portion is provided between each pair of contiguous metal fill structures

Methodology Applied

Scientific EffectDielectric material: Dielectric

Data Source

PatentUS8138607B2Metal fill structures for reducing parasitic capacitance

Publication Date: 2012.03.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Vertically-staggered-level metal fill structures include inner contiguous metal fill structures and outer contiguous metal fill structures. A dielectric material portion is provided between each contiguous metal fill structure. Vertical extent of each contiguous metal fill structure is limited up to three vertically adjoining metal interconnect levels, thereby limiting the capacitance of each contiguous metal fill structure. Capacitive coupling between the contiguous metal fill structures and the metal interconnect structures is minimized due to the fragmented structure of contiguous metal fill structures.