Staggered Active Bitline Sensing for NAND Interference Reduction
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Solution Overview
Problem
Multi-level NAND-type flash memory experiences read errors due to slight threshold voltage shifts and interference from neighboring bitlines, especially in penta-level cell encoding, leading to performance degradation.
Innovation Solution
Implementing staggered active bitline sensing by applying separate control signals to even and odd bitlines with a stagger time period to reduce noise and interference, ensuring accurate and efficient reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If simultaneous sensing on all bitlines is performed, then read time is reduced, but read errors increase due to neighboring bitline interference
Solution Approach 1:
The patent divides the bitline sensing operation into two separate segments: even bitlines are sensed during a first time period while odd bitlines are sensed during a second time period. This temporal segmentation eliminates simultaneous sensing interference between neighboring bitlines, resolving the contradiction between fast read time and high read accuracy.
2Quantity of substance
If penta-level cell encoding is used to increase storage capacity, then bits per cell increase, but threshold voltage shifts cause more read errors
Solution Approach 1:
By segmenting the sensing operation into separate time periods for even and odd bitlines, the patent eliminates coupling noise that would otherwise cause threshold voltage shifts. This allows penta-level cell encoding to achieve 5 bits per cell storage capacity while maintaining read accuracy through interference-free sensing.
3Reliability
If staggered sensing is implemented to reduce interference, then read errors decrease, but read time increases
Solution Approach 1:
The patent merges the sensing operations of even and odd bitlines into a unified multi-phase process that uses shared sense amplifiers and control logic. By reusing hardware resources across the two time periods and efficiently managing the sensing phases, the patent minimizes the overall read time penalty while maintaining the interference-reduction benefits of staggered sensing.
Data Source
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AI summary
Systems, apparatuses and methods may provide for technology that applies a first set of control signals to even bitlines in NAND memory and senses voltage levels of the even bitlines during an even sensing time period. The technology may also apply a second set of control signals to odd bitlines in the NAND memory, and sense voltage levels of the odd bitlines during an odd sensing time period, wherein the second set of control signals are applied after expiration of a stagger time period between the even sensing time period and the odd sensing time period.