Staggered NAND Flash Command Execution for Peak Power Reduction
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Solution Overview
Problem
Multi-chip NAND flash memory devices experience a sudden increase in power consumption when executing global memory commands, which can overwhelm the power supply and affect device performance, especially in battery-powered applications.
Innovation Solution
Implementing a timing mechanism that staggers the execution of global memory commands across multiple NAND flash memories, using a timer to introduce a time delay that increases with each subsequent memory, ensuring that not all memories initiate the command simultaneously, thereby reducing peak power demand.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If global memory commands are executed simultaneously by all NAND flash memories, then command execution efficiency is improved, but peak power consumption increases significantly
Solution Approach 1:
The patent implements periodic action by introducing a time delay mechanism that staggers the execution of global memory commands across multiple NAND flash memories. Each memory device executes the command at different time intervals rather than simultaneously, which distributes the power consumption over time and reduces peak power demand while still achieving command execution across all devices
Solution Approach 2:
The patent applies preliminary action by having the first NAND flash memory execute the global command immediately without delay, while subsequent memories are pre-configured with increasing time delays. This ensures that at least one memory is always executing the command, maintaining system productivity while the staggered execution of other memories reduces peak power consumption
2Quantity of substance
If multiple NAND flash memories are packaged together as a multi-chip device, then memory density is increased, but peak power demand on the power supply increases
Solution Approach 1:
The patent uses periodic action to distribute the power demand of multiple packaged memories over time. By implementing time delays that increase with each subsequent memory device, the system maintains high memory density while reducing the simultaneous power demand that would otherwise overwhelm the power supply
3Speed
If all NAND flash memories execute a global command at the same time, then the command is completed faster, but voltage dips occur affecting device performance
Solution Approach 1:
The patent applies preliminary action by having the first memory execute the command immediately, ensuring the command starts without delay. Subsequent memories are then activated with increasing time delays, which prevents simultaneous execution and the resulting voltage dips, thereby maintaining device performance stability while still achieving relatively fast command completion
Data Source
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AI summary
System and method for executing a global memory command in a multi-chip non-volatile memory device having a plurality of non-volatile memories. The global memory command is received at each non-volatile memory concurrently. The memory command is initiated at different times relative to receiving the global memory command for at least two of the plurality of non-volatile memory to mitigate peak power consumption.