Staggered 3D NAND Read Recovery for Read Window Budget Loss

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Solution Overview

Problem

3D NAND flash memory devices face read window budget (RWB) degradation due to threshold voltage (Vt) shift and cell-to-cell variation, exacerbated by temperature changes and random telegraph noise, which traditional methods struggle to address effectively.

Innovation Solution

Implementing a staggered read recovery process where wordlines in a 3D NAND array are transitioned to ground sequentially after a read operation, providing a grounding path for charge dissipation and reducing trapped charges at grain boundaries.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If all wordlines are transitioned to ground simultaneously after a read operation, then the read operation is simple and fast, but charge traps at grain boundaries cause RWB degradation due to incomplete charge discharge

Engineering Contradiction:
Improveread operation speedVSAvoidread window budget
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the wordline grounding process into multiple stages. Instead of grounding all wordlines simultaneously, the controller grounds wordlines in sequential groups (e.g., first group of wordlines, then second group of wordlines). This segmentation allows charges to discharge more completely from charge traps at grain boundaries while maintaining reasonable read operation speed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies a preliminary action by introducing a delay period between the read operation and the grounding of wordlines. The controller waits for a predetermined time after the read operation before initiating the grounding sequence. This preliminary delay allows charges to begin discharging from charge traps before the wordlines are fully grounded, improving RWB without significantly impacting read speed.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If smaller program steps are used to compensate for RWB loss, then RWB degradation is reduced, but programming time increases

Engineering Contradiction:
Improveread window budgetVSAvoidprogramming time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by grounding wordlines before the programming operation is complete. The controller grounds wordlines in a predetermined sequence after the read operation, which prepares the charge distribution in advance for subsequent programming operations. This reduces the need for smaller program steps and decreases overall programming time while maintaining RWB.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If operating temperature range is limited to reduce RWB loss, then temperature-induced Vt shift is reduced, but use cases and deployment are significantly limited

Engineering Contradiction:
Improveread window budgetVSAvoidoperating temperature range
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent segments the charge discharge process by grounding wordlines in multiple sequential groups rather than simultaneously. This segmentation allows charges to discharge gradually from charge traps at grain boundaries, reducing temperature-induced Vt shift effects. The controller can maintain a wider operating temperature range while preserving RWB through this segmented grounding approach.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances read noise reduction and temperature sensitivity, improving 3D NAND performance and enabling continued scaling by minimizing RWB degradation.

Implementation Method 1

transitioning the wordlines to ground in a staggered manner provides a grounding path for charge dissipation

Methodology Applied
Scientific EffectCharge dissipation: Conduction (electrical)

Data Source

PatentUS20250349342A1Staggered read recovery for improved read window budget in a three dimensional (3D) NAND memory array
Publication Date: 2025.11.13 INTEL NDTM US LLC
  • US20250349342A1 patent drawing
  • US20250349342A1 patent drawing
  • US20250349342A1 patent drawing

AI summary

After reading a 3D (three dimensional) NAND array, the wordlines of the 3D NAND array can be transitioned to ground in a staggered manner. The 3D NAND array includes a 3D stack with multiple wordlines vertically stacked, including a bottom-most wordline, a top-most wordline, and middle wordlines between the bottom-most wordline and the top-most wordline. A controller that controls the reading can set the multiple wordlines to a read voltage for reading operations and then transition a selected wordline of the multiple wordlines from the read voltage to ground prior to transitioning the other wordlines to ground. Thus, the controller will transition the other wordlines from the read voltage to ground after a delay.