Staggered Nano-Fin Array for High-Density Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor memory devices face yield loss and imperfect connections due to 'pattern-mismatch' when using normal photolithographic and sub-photolithographic groundrule structures, which affects the density and performance of memory devices.
Innovation Solution
A nano-fin array structure with staggered nano-fins, each with multiple gates and regions, where the nano-fins are electrically connected to common contacts and feature sub-photolithographic dimensions, allowing for efficient control of conductance and integration with memory elements like anti-fuses or DRAM cells, while avoiding the limitations of conventional lithographic pitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If normal photolithographic groundrule and sub-photolithographic groundrule structures are used in the same structure, then memory device density is increased, but pattern-mismatch occurs causing yield loss and imperfect connections
Solution Approach 1:
The invention divides the memory device into distinct first and second portions, each utilizing different groundrule dimensions (normal photolithographic for the first portion, sub-photolithographic for the second portion). This segmentation allows each portion to be optimized independently, enabling high density in the second portion while maintaining manufacturing reliability in the first portion, thus resolving the pattern-mismatch problem.
2Quantity of substance
If sub-photolithographic groundrule structures are used, then memory device density is increased, but manufacturing precision deteriorates due to pattern-mismatch
Solution Approach 1:
The memory device is segmented into two distinct portions with different groundrule specifications. The first portion uses normal photolithographic groundrules for manufacturable precision, while the second portion uses sub-photolithographic groundrules for high density. The interface between portions is designed to accommodate the transition, preventing pattern-mismatch from degrading overall manufacturing precision.
3Manufacturing precision
If normal photolithographic groundrule structures are used, then manufacturing precision is maintained, but memory device density is limited
Solution Approach 1:
The invention transitions from a uniform two-dimensional photolithographic structure to a hybrid structure that incorporates sub-photolithographic dimensions in the second portion. This dimensional change enables higher density by breaking through the conventional photolithographic groundrule limits, while the first portion maintains traditional dimensions for manufacturing precision.
Data Source
AI summary
A structure, memory devices using the structure, and methods of fabricating the structure. The structure includes: an array of nano-fins, each nano-fin comprising an elongated block of semiconductor material extending axially along a first direction, the nano-fins arranged in groups of at least two nano-fins each, wherein ends of nano-fins of each adjacent group of nano-fins are staggered with respect to each other on both a first and a second side of the array; wherein nano-fins of each group of nano-fins are electrically connected to a common contact that is specific to each group of nano-fins such that the common contacts comprise a first common contact on the first side of the array and a second common contact on the second side of the array; and wherein each group of nano-fins has at least two gates that electrically control the conductance of nano-fins of the each group of nano-fins.