Staggered Pad ESD Protection Circuit Layout
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Solution Overview
Problem
Conventional semiconductor chips face limitations in size reduction due to the size and arrangement of electrostatic discharge (ESD) protection circuits, which restrict the number of pads and increase the vertical size of the chip, especially as the number of pads increases and higher voltage processes require larger ESD protection circuits.
Innovation Solution
The semiconductor chip design includes a staggered or zigzag arrangement of pads with ESD protection circuits, where the second ESD protection circuit is connected to a conducting layer between outer pads and neighbors the first pad on the outer side, allowing for a reduced chip size while maintaining effective ESD protection by arranging diodes under the pads and using a conductive layer to connect them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of pads is increased to improve chip functionality, then the chip's I/O capability is improved, but the chip size increases due to the larger ESD protection circuits required
Solution Approach 1:
The patent merges the ESD protection circuits for multiple pads into a shared structure. Specifically, the first and second ESD protection circuits are combined and arranged under a single outer pad, allowing multiple pads to share common ESD protection resources. This reduces the total area occupied by ESD protection circuits while maintaining protection for all pads, thereby enabling increased I/O capability without proportional increase in chip size.
Solution Approach 2:
The shared ESD protection circuit structure serves multiple pads simultaneously, making the ESD protection mechanism universal. The first and second ESD protection circuits, when combined, provide protection for both the first pad (connected to outer pad) and the second pad (connected to inner pad), allowing a single ESD protection structure to fulfill multiple protective functions.
2Reliability
If the ESD protection circuit size is increased to protect against higher voltage processes, then the ESD protection capability is improved, but the vertical size of the chip increases
Solution Approach 1:
The patent transitions the ESD protection circuit arrangement from a vertical stacking approach to a horizontal planar arrangement. Instead of placing ESD protection circuits vertically under each pad (which increases vertical chip size), the circuits are arranged horizontally under outer pads in a staggered or zigzag pattern. This dimensional change allows higher voltage ESD protection without increasing the chip's vertical dimension.
Solution Approach 2:
The patent applies ESD protection circuits selectively at specific locations rather than uniformly across all pads. The first and second ESD protection circuits are arranged under outer pads where they can provide protection for multiple pads through the shared structure. This localized arrangement optimizes the distribution of ESD protection resources, providing enhanced protection capability without uniform increase in vertical chip size.
3Quantity of substance
If the pads are arranged in a staggered structure to increase pad density, then the number of pads per area is improved, but the ESD protection circuit arrangement becomes more complex
Solution Approach 1:
The patent employs an asymmetric staggered or zigzag arrangement of pads rather than a symmetric grid pattern. This asymmetric arrangement allows outer pads to be positioned such that their ESD protection circuits can share space more efficiently. The irregular positioning creates opportunities for overlapping ESD protection circuit footprints, reducing overall complexity compared to arranging ESD circuits separately under each pad in a symmetric layout.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This layout enables an increase in the number of pads without compromising ESD protection, reducing the chip size by optimizing the placement and connection of ESD protection circuits, thereby minimizing size limitations imposed by the ESD protection circuit.
Implementation Method 1
When static electricity is introduced through the pads, the ESD protection circuit protects circuits inside or on (e.g., the main circuit) of the semiconductor chip against the static electricity by discharging the static electricity through a designated path
Implementation Method 2
The second ESD protection circuit may be connected to a conducting layer between the two pads formed on the outer side of the semiconductor chip
Data Source
AI summary
A semiconductor chip may include a plurality of pads arranged in at least a first and a second row, and a plurality of protection circuits connected to the plurality of pads. The plurality of protection circuits may include at least one diode. A first protection circuit may be connected to a first pad in the first row of pads, and a second protection circuit may be connected to a second pad in the second row of pads. The first and second protection circuits may be arranged under the first row of pads.