Staggered Pad Arrangement for Semiconductor Chip Area Reduction
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Solution Overview
Problem
The increasing number of transistors in semiconductor integrated circuits leads to a larger chip area due to the need for input/output cells and wire bonding, limiting miniaturization and increasing manufacturing costs, as conventional flip-chip structures require extensive interconnects that can compromise timing performance.
Innovation Solution
The semiconductor integrated circuit device employs a design where pads on the semiconductor chip are arranged in a rectangular dot grid pattern in the center and a staggered dot pattern in the corners, with interconnects routed at an angle to reduce chip area and improve electrical characteristics, allowing efficient routing and reduced manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If pads are arranged in a rectangular dot grid pattern in the center and staggered dot pattern in the corners, then interconnect lengths are shortened and chip area is reduced, but routing complexity increases
Solution Approach 1:
The patent applies asymmetry by using a rectangular dot grid pattern for pads in the center region and a staggered dot pattern for pads in the corner regions. This asymmetric arrangement allows interconnects to be routed more efficiently, shortening their lengths while managing routing complexity through region-specific patterns.
Solution Approach 2:
The patent segments the chip into different regions (center region with rectangular grid pattern and corner regions with staggered pattern) to optimize interconnect routing in each region. This segmentation allows tailored pad arrangements that reduce overall interconnect length while distributing routing complexity across manageable regions.
2Productivity
If the number of transistors is increased, then circuit functionality is improved, but chip area increases due to input/output cells and wire bonding requirements
Solution Approach 1:
The patent replaces the conventional wire bonding method with a flip-chip bump bonding method. This substitution eliminates the need for peripheral input/output cells and their associated wire bonding area, allowing increased transistor density without proportional increases in chip area.
Solution Approach 2:
The patent transitions from two-dimensional peripheral I/O cell arrangement to a three-dimensional flip-chip architecture where bumps connect the chip underside to the substrate. This dimensional change allows I/O cells to be distributed across the entire chip area rather than confined to the periphery, enabling higher transistor counts without increasing chip area.
3Reliability
If wire bonding method is used, then connection between LSI and package is achieved, but input/output cells require predetermined size to maintain strength during press-bonding
Solution Approach 1:
The patent replaces wire bonding with bump bonding technology. This substitution eliminates the need for large input/output cells required for wire press-bonding, as bumps provide sufficient mechanical strength and electrical connection with minimal cell area, thereby reducing overall chip area while maintaining connection reliability.
4Device complexity
If pads are arranged on the entire surface of the chip in flip-chip manner, then wiring between pads and input/output cells is eliminated, but number of interconnects and their length increase
Solution Approach 1:
The patent uses asymmetric pad arrangements with rectangular grid patterns in the center and staggered patterns in the corners. This asymmetry optimizes interconnect routing paths, reducing overall interconnect lengths while maintaining the simplified flip-chip architecture that eliminates complex wiring between pads and input/output cells.
Solution Approach 2:
The patent applies different pad patterns in different regions (rectangular grid in center, staggered in corners) to locally optimize interconnect lengths. This local quality approach reduces interconnect lengths in specific regions while maintaining the overall benefits of the flip-chip structure.
Data Source
AI summary
A semiconductor integrated circuit device includes a semiconductor chip including input/output cells, pads formed on a surface of the semiconductor chip, and interconnects formed on the surface of the semiconductor chip to electrically connect at least some of the plurality of input/output cells and at least some of the plurality of pads. A first plurality of the pads located in a center portion of the semiconductor chip are arranged in a rectangular dot grid pattern, and a second plurality of the pads located in at least one of four corner portions of the semiconductor chip are arranged in a staggered dot pattern.