Staggered PoP Connectors Reduce Thermal Strain
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Solution Overview
Problem
Package on Package (PoP) structures experience increased ball strain and connector defects during thermal cycling due to substrate thinning and warpage, leading to circuit failures and reduced reliability.
Innovation Solution
Implementing a staggered pattern for external connectors relative to the PoP connectors, and optionally using a molded underfill layer, to reduce thermal and mechanical stress, and removing corner connectors in the external array to alleviate strain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If substrate thickness is reduced to save space, then package size is reduced, but ball strain and connector reliability worsen due to increased warpage
Solution Approach 1:
The patent applies asymmetry by implementing a staggered pattern where external connectors are offset from PoP connectors, creating an asymmetric layout that disrupts the alignment of stress pathways. This asymmetric arrangement prevents concentrated strain at aligned connector interfaces, thereby improving reliability while maintaining reduced package size
Solution Approach 2:
The patent addresses the two-dimensional connector layout problem by introducing a dimensional offset in the vertical stacking arrangement. The staggered pattern creates non-coincident connector positions across layers, effectively adding a positional dimension to the connector arrangement that distributes thermal and mechanical stress more evenly throughout the package structure
2Area of stationary object
If PoP structure is used to reduce board area, then board space is reduced, but ball strain increases during thermal cycling
Solution Approach 1:
The staggered connector pattern creates an asymmetric stress distribution that prevents ball strain concentration. By offsetting external connectors from PoP connectors, the design breaks the vertical alignment of stress pathways, distributing thermal cycling stress more evenly across the package structure while maintaining the compact PoP configuration
Solution Approach 2:
The patent introduces an intermediary staggered connector arrangement that mediates between the PoP connectors and the board. This intermediate layer of connectors absorbs and redistributes thermal and mechanical stress, preventing direct stress transmission from the board through aligned connector paths to the PoP structure
3Adaptability or versatility
If connector count is maintained to preserve functionality, then connectivity is maintained, but strain on connectors increases
Solution Approach 1:
The staggered pattern maintains full connector functionality while distributing stress asymmetrically across the connector array. By offsetting connector positions between PoP and external layers, the design preserves all necessary electrical connections while preventing strain concentration, effectively maintaining connectivity without compromising connector strength
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The staggered pattern and underfill layer reduce connector strain by up to 50% during thermal cycle testing, and the corner removal reduces strain by approximately 10%, enhancing the reliability and durability of PoP structures without altering the connector count or package size.
Implementation Method 1
The staggered pattern and underfill layer reduce connector strain by up to 50% during thermal cycle testing
Implementation Method 2
During thermal cycling tests, ball strain has been observed in PoP packages. This ball strain can cause the connector terminals, such as solder balls, to crack or lift off of the conductive pads
Implementation Method 3
During thermal cycling tests, ball strain has been observed in PoP packages
Data Source
AI summary
Methods and apparatus for package on package structures. A structure includes a first integrated circuit package including at least one integrated circuit device mounted on a first substrate, a plurality of package on package connectors extending from a bottom surface and arranged in a pattern of one or more rows proximal to an outer periphery of the first substrate; and a second integrated circuit package including at least another integrated circuit device mounted on a second substrate and a plurality of lands on an upper surface coupled to the plurality of package on package connectors, and a plurality of external connectors extending from a bottom surface of the second substrate; wherein the pattern of the external connectors is staggered from the pattern of the package on package connectors so that the package on package connectors are not in vertical alignment with the external connectors. Methods for forming structures are disclosed.