Staggered Power Array Drain Layout for Thermal Management
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Solution Overview
Problem
High voltage devices face a tradeoff between breakdown voltage and on-resistance, with existing designs struggling to maintain low on-resistance while achieving high breakdown voltage and a robust safe operating area, especially due to thermal issues affecting reliability.
Innovation Solution
A power array with a staggered arrangement of device units, where each drain region is offset in the row direction from adjacent drain regions, increasing the distance between them and thereby reducing heat accumulation and enhancing the safe operating area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If device units are arranged in a conventional aligned manner, then manufacturing is simpler, but heat accumulation occurs in adjacent drain regions leading to reduced reliability and smaller safe operating area
Solution Approach 1:
The patent applies asymmetry by staggering the drain regions of adjacent device units in a triangular pattern rather than aligning them symmetrically. This asymmetric arrangement increases the distance between adjacent drain regions, reducing heat accumulation and improving the safe operating area and reliability of the power array.
2Strength
If breakdown voltage is increased, then device can handle higher voltages, but on-resistance increases reducing efficiency
Solution Approach 1:
The patent applies local quality by optimizing the doping concentration and layer structure in specific regions of the device. The drift region is designed with graded doping to locally enhance breakdown voltage where needed, while maintaining low on-resistance in the channel region, thus resolving the tradeoff between these two parameters.
Data Source
AI summary
A power array with a staggered arrangement for improving on-resistance and safe operating area of a device is provided. Each power array includes two or more rows with a plurality of parallel device units arranged along the row. Each device unit includes a source region, a drain region, and a gate disposed between the source region and the drain region, wherein each drain region is offset from the adjacent drain region of adjacent rows in a row direction.