Staggered Power Distribution Network for Low Profile Packages
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Solution Overview
Problem
In high-speed signal chip design, power delivery structures face challenges in providing stable and balanced power support due to parasitic effects in low profile packages with closely spaced interconnects, which complicates the design of thinner dies and chips.
Innovation Solution
A power distribution structure is implemented by dividing metal layers into staggered island regions, minimizing overlaps between interconnects from different netlists, and utilizing vias to couple regions across layers, thereby maximizing surface area coverage and reducing parasitic effects, inductance, and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If interconnects are placed close together to reduce package profile, then package thickness is reduced, but parasitic effects increase
Solution Approach 1:
The patent divides the package substrate into multiple distinct regions (first region, second region, third region) with different interconnect arrangements. Each region has specifically designed metal layer configurations that segment the overall power distribution network, allowing optimization of parasitic characteristics in each zone while maintaining thin profile overall.
Solution Approach 2:
Different regions of the package substrate are assigned different interconnect densities and metal layer configurations. The first region has a specific arrangement of interconnects and metal layers optimized for certain performance characteristics, while the second and third regions have different arrangements optimized for other characteristics, allowing local optimization of parasitic effects.
2Reliability
If multiple metal layers are used to provide stable power delivery, then power stability is improved, but device complexity increases
Solution Approach 1:
The power distribution network is segmented into different functional regions with specific metal layer assignments. First metal layers and second metal layers are used in different regions according to specific patterns, reducing the need for uniform high-layer-count designs across the entire substrate while maintaining power stability.
Solution Approach 2:
The patent utilizes the vertical dimension by strategically assigning first metal layers and second metal layers to different regions. This dimensional approach allows power delivery optimization through layer selection rather than simply adding more layers uniformly, managing complexity through spatial distribution.
3Object-generated harmful factors
If interconnects are spaced further apart to reduce parasitic effects, then parasitic effects are reduced, but surface area coverage decreases
Solution Approach 1:
The substrate is divided into regions with different interconnect spacing optimizations. Some regions have closer spacing to maximize coverage, while other regions have wider spacing to minimize parasitic effects. This segmentation allows the system to achieve both goals in different zones rather than compromising either objective globally.
Solution Approach 2:
Different regions implement different interconnect spacing strategies based on local requirements. The first region, second region, and third region each have optimized spacing arrangements that balance coverage and parasitic reduction locally, allowing the overall system to achieve both high coverage and low parasitic effects.
Data Source
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AI summary
Some novel features pertain to an integrated device that includes a first metal layer and a second metal layer. The first metal layer includes a first set of regions. The first set of regions includes a first netlist structure for a power distribution network (PDN) of the integrated device. The second metal layer includes a second set of regions. The second set of regions includes a second netlist structure of the PDN of the integrated device. In some implementations, the second metal layer further includes a third set of regions comprising the first netlist structure for the PDN of the integrated device. In some implementations, the first metal layer includes a third set of regions that includes a third netlist structure for the PDN of the integrated device. The third set of regions is non-overlapping with the first set of regions of the first metal layer.