Staggered Power-Ground Pair Wiring for Resonance Suppression
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Solution Overview
Problem
High-frequency signals in semiconductor integrated circuits face challenges with parasitic inductance and resonance in power and ground wiring, leading to difficulties in stable charge supply and discharge, especially in high-speed applications beyond 10 GHz, where current limitations and electromagnetic interference (EMI) issues arise.
Innovation Solution
A pair wiring structure is implemented where power source and ground wirings are juxtaposed at a predetermined interval within the semiconductor integrated circuit package and printed circuit board, establishing electromagnetic coupling to prevent resonance and ensure stable power supply, with the addition of bypass capacitors to manage frequency characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If solid (plane) power supply and solid (plane) ground are disposed to avoid current limitation, then power supply capability is improved, but resonance occurs in high-frequency bandwidth causing EMI problems
Solution Approach 1:
The patent segments the power supply and ground connections into multiple distributed via holes instead of using solid planes. This segmentation allows the power and ground to be supplied through multiple discrete points, avoiding the resonance issues of solid planes while maintaining adequate power delivery capability through the distributed arrangement of multiple via connections.
2Speed
If decoupling capacitor is inserted close to switch circuit as built-in component, then charge supply speed is improved, but there is a limit to the degree of proximity
Solution Approach 1:
The patent embeds the decoupling capacitor functionality within the package structure itself, nesting the capacitor between the semiconductor chip and the substrate. This allows the decoupling function to be integrated closely with the switch circuit while utilizing the three-dimensional space within the package, achieving high-speed charge supply without excessive planar complexity.
3Ease of operation
If power source and ground wirings extend to decoupling capacitor forming transmission line, then charge supply path is established, but current limitation is imposed by characteristic impedance
Solution Approach 1:
The patent transitions from two-dimensional planar wiring to three-dimensional vertical via connections. By stacking via holes vertically through multiple layers to reach the decoupling capacitor, the patent reduces the effective path length and characteristic impedance effects, enabling higher current capability while maintaining adequate charge supply paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses resonance in high-frequency bandwidths, enabling stable power and ground wiring, supporting high-speed operations without current limitations, and reducing electromagnetic interference, thus ensuring reliable operation of semiconductor integrated circuits.
Implementation Method 1
electromagnetic coupling is established between the power source wiring and the ground wiring, wherefore a transmission line structure can be obtained
Data Source
AI summary
A semiconductor integrated circuit package, a printed circuit board, a semiconductor apparatus, and a power supply wiring structure that allow attainment of stable power source and ground wiring without causing resonance even in a high-frequency bandwidth are provided. In an interior portion of the package, a power source wiring and a ground wiring constitute a pair wiring structure in which the power source wiring and the ground wiring are juxtaposed at a predetermined interval so as to establish electromagnetic coupling therebetween. A plurality of pair wiring structures are combined in such a manner that, when viewed in a section perpendicular to a wiring extending direction, the pair wiring assembly assumes a staggered (checkered) configuration. It is preferable that, each of the silicon chip and the printed circuit board, like the package, has pair wiring structures disposed inside.