Staggered Refresh Counters for Memory Devices
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Solution Overview
Problem
In memory devices, concurrent refresh operations in edge sections can cause power and current spikes due to the simultaneous activation of more word lines, leading to increased peak power and current consumption, which is undesirable.
Innovation Solution
Implementing staggered refresh counters across memory dies, where each die has a unique refresh counter value offset by the number of rows in each section, ensuring that not all dies refresh edge sections at the same time, even when sharing a command/address bus. This is achieved through fuse circuitry that initializes and maintains offset values during operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If concurrent refresh operations are performed in edge sections, then refresh completeness is improved, but peak power and current consumption increase
Solution Approach 1:
The patent implements staggered periodic refresh operations across multiple memory dies, where each die has an offset refresh counter that causes refresh operations to be distributed over time. This periodic staggering maintains complete refresh coverage while reducing peak power and current consumption by preventing simultaneous edge section refreshes across all dies.
Solution Approach 2:
The patent segments the refresh operation by dividing memory dies into groups with different refresh counter offsets. Each die is assigned a unique offset value that segments the overall refresh timeline, causing edge section refreshes to occur at different times across segments rather than concurrently, thereby reducing peak power demands.
2Reliability
If concurrent refresh operations are performed in edge sections, then refresh coverage is maintained, but current spikes increase
Solution Approach 1:
The staggered refresh counter mechanism creates periodic refresh patterns with temporal separation. Each memory die performs refresh operations at periodically spaced intervals with unique offsets, ensuring all sections are covered over time while current spikes are distributed and reduced in magnitude compared to concurrent operations.
Solution Approach 2:
The patent applies preliminary action by pre-configuring offset values in fuse circuitry before operation. These pre-established offsets determine the staggered timing of refresh operations, allowing the system to proactively avoid current spikes by ensuring edge section refreshes are distributed across different time periods.
3Power
If staggered refresh counters are implemented, then peak power consumption is reduced, but device complexity increases
Solution Approach 1:
The staggered refresh counter system is self-configuring through fuse circuitry that automatically establishes unique offset values for each memory die during manufacturing. Once programmed, the system autonomously maintains staggered refresh timing without requiring external control or complex configuration logic, reducing operational complexity despite the staggered architecture.
Solution Approach 2:
The patent introduces an intermediary mechanism in the form of offset values that mediate between the refresh command signal and the actual refresh execution. These offset intermediaries, stored in fuse circuitry, translate a single refresh command into staggered execution times across different dies, simplifying the control architecture while achieving power reduction.
Data Source
AI summary
Methods, systems, and devices for staggered refresh counters for a memory device are described. The memory device may include a set of memory dies each coupled with a common command and address (CA) bus and each including a respective refresh counter. In response to a refresh command received over the CA bus, each memory die may refresh a set of memory cells based on a value output by the respective refresh counter for the memory die. The refresh counters for at least two of the memory dies of the memory device may be offset such that they indicate different values when a refresh command is received over the CA bus, and thus at least two of the memory dies may refresh memory cells in different sections of their respective arrays. Offsets between refresh counters may be based on different fuse settings associated with the different memory dies.