Staggered Refresh Signal Delay in Stacked Semiconductor Memory
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Solution Overview
Problem
Conventional semiconductor memory apparatuses experience power noise during refresh operations, which can disrupt data preservation when multiple chips are stacked and simultaneously activated, leading to incomplete or failed refresh operations.
Innovation Solution
A semiconductor memory apparatus is designed with a refresh signal generation unit in the first chip and delay units in subsequent stacked chips, where each chip delays and relays the refresh signal through through-silicon vias, allowing each chip to perform refresh operations at different times, thereby preventing simultaneous activation and power noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple chips are stacked and simultaneously activated to increase memory capacity and decrease occupied area, then memory capacity increases and occupied area decreases, but power noise occurs during refresh operations disrupting data preservation
Solution Approach 1:
The refresh operation is segmented across multiple chips by introducing different delay times for each chip. The first chip performs refresh at time T, the second chip at T+d1, the third chip at T+d1+d2, and so on. This segmentation prevents simultaneous refresh operations across all chips, eliminating power noise while maintaining data preservation for all chips in the stacked configuration.
Solution Approach 2:
Delay units are introduced in each chip to preliminarily delay the refresh signal before it reaches the core region. The first delay unit delays the refresh signal by a first delay time, the second delay unit by a second delay time, and so on. This preliminary action ensures that refresh operations are staggered in time, preventing power noise before it can occur.
2Quantity of substance
If multiple chips are stacked and simultaneously activated, then memory capacity increases, but power noise occurs during refresh operations
Solution Approach 1:
The refresh operation is segmented across multiple chips by introducing different delay times for each chip. The first chip performs refresh at time T, the second chip at T+d1, the third chip at T+d1+d2, and so on. This segmentation prevents simultaneous refresh operations across all chips, eliminating power noise while maintaining data preservation for all chips in the stacked configuration.
Solution Approach 2:
Refresh operations are transformed from simultaneous periodic actions into staggered periodic actions. Each chip performs refresh operations at different time intervals based on its specific delay time, converting the harmful simultaneous periodic action into beneficial staggered periodic actions that eliminate power noise.
3Object-generated harmful factors
If refresh signals are delayed and relayed through through-silicon vias, then power noise is prevented, but device complexity increases
Solution Approach 1:
Delay units are introduced as intermediary components between the refresh signal input and the core region in each chip. These delay units serve as mediators that stagger the timing of refresh signals across different chips, preventing power noise while adding minimal complexity to the overall device architecture.
Data Source
AI summary
A semiconductor memory apparatus includes a first chip including a refresh signal generation unit which is configured to receive an external command and generate a refresh signal; and a second chip including a first delay unit which is configured to receive the refresh signal through a first through-silicon via and delay the received refresh signal, a first selection unit which is configured to output an output signal of the first delay unit to the first chip through a second through-silicon via in response to a first select signal, and a first core region which is configured to receive the output signal of the first delay unit and perform a refresh operation.