Staggered Refresh Timing for Memory Bank Power Control

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Solution Overview

Problem

As memory components decrease in size, the increased density of memory cells leads to data degradation due to 'row hammer' effects, where repeated access to a particular memory cell affects nearby cells, necessitating targeted refresh operations to prevent information loss, while auto-refresh operations consume more power and may not address victim rows in time.

Innovation Solution

The solution involves staggering the timing of targeted and auto-refresh operations across memory banks, using a refresh control circuit to generate staggered refresh addresses and pump signals, allowing some banks to perform targeted refreshes while others perform auto-refreshes simultaneously, thereby controlling peak power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If targeted refresh operations are performed to address row hammer effects, then data integrity is improved, but power consumption increases

Engineering Contradiction:
Improvedata integrityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The memory device is divided into multiple memory banks that can perform refresh operations independently. The refresh control circuit segments the refresh tasks into targeted refresh operations (for victim rows affected by row hammer) and auto-refresh operations (for all rows), distributing these tasks across different memory banks to manage power consumption while ensuring data integrity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs refresh operations periodically, alternating between targeted refresh operations and auto-refresh operations. The refresh control circuit manages the timing of these periodic operations to ensure that victim rows are refreshed at appropriate intervals without causing excessive power consumption, extending the time between auto-refresh cycles.

Inventive Principle:
Principle #19Periodic action

2Reliability

If multiple memory banks perform refresh operations simultaneously, then data integrity is maintained, but peak power consumption increases

Engineering Contradiction:
Improvedata integrityVSAvoidpeak power consumption
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

The refresh control circuit implements periodic staggering of refresh operations across memory banks. Not all memory banks perform refresh operations at the same time; instead, they are timed periodically so that some banks perform targeted refreshes while others perform auto-refreshes simultaneously, reducing peak power consumption while maintaining data integrity through coordinated operation.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The system dynamically adjusts which memory banks perform which type of refresh operation based on real-time needs. The refresh control circuit can dynamically assign targeted refresh tasks to specific banks while others perform auto-refreshes, creating a dynamic load distribution that reduces peak power consumption while ensuring all data is properly refreshed.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11309012B2Apparatuses and methods for staggered timing of targeted refresh operations
Publication Date: 2022.04.19 MICRON TECHNOLOGY INC
  • US11309012B2 patent drawing
  • US11309012B2 patent drawing
  • US11309012B2 patent drawing

AI summary

Embodiments of the disclosure are drawn to apparatuses and methods for staggering the timing of targeted refresh operations. A memory device may include a number of memory banks, at least some of which may be simultaneously entered into a refresh mode. A given memory bank may perform an auto-refresh operation or a targeted refresh operation, which may draw less power than the auto-refresh operation. The timing of the targeted refresh operations may be staggered between the refreshing memory banks, such that a portion of the refreshing memory banks are performing a targeted refresh operation simultaneously with a portion of the refreshing memory banks performing an auto-refresh operation.