Staggered Refresh Timing in Stacked Memory Chips

The patent segments the refresh operation timing across multiple memory chips by introducing chip-specific delay values. Each chip in the stacked package performs refresh operations at different time points rather than simultaneously, dividing the集中 current consumption into distributed temporal segments. This is achieved through a delay unit that adds chip identification-based delay periods to refresh commands for each respective chip.

The patent implements periodic refresh operations with staggered timing for different chips. Each memory chip receives refresh commands at periodic intervals, but the periods are offset by chip-specific delay values. This ensures that all chips are refreshed periodically for data retention while preventing simultaneous peak current draws through temporal distribution of the periodic actions.

The patent enables each memory chip to autonomously manage its own refresh timing based on its chip identification. The delay unit within each chip automatically calculates and applies the appropriate delay value based on its unique ID, eliminating the need for complex external timing control circuitry. This self-service approach distributes the timing complexity to individual chips rather than requiring centralized complex control.