Staggered Scan Chain Clocking for Peak Power Reduction
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Solution Overview
Problem
In semiconductor integrated circuits, the peak power increase during testing due to simultaneous operation of multiple flip-flops in a scan chain leads to local voltage drops, causing test failures and potentially misidentifying functional circuits as defective.
Innovation Solution
The semiconductor device employs a clock control circuit that supplies different clocks to orthogonal scan chains, allowing only a maximum of two flip-flops per power supply line to operate simultaneously, thereby reducing peak power and local voltage drops by staggering the operation timing of the scan chains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple scan chains operate simultaneously during testing, then testing productivity is improved, but peak power increases and local voltage drops occur
Solution Approach 1:
The patent applies periodic action by dividing scan chains into multiple groups and assigning different clock phases to each group. This causes flip-flops in different groups to operate at different time periods, transforming the simultaneous operation into a periodic, staggered operation pattern that reduces peak power while maintaining overall testing productivity.
Solution Approach 2:
The patent segments the scan chains into multiple groups (first group, second group, etc.) and assigns different clock signals to each group. This segmentation allows independent control of operation timing for different segments, enabling reduced peak power consumption while maintaining comprehensive testing coverage.
2Productivity
If multiple scan chains operate simultaneously during testing, then testing productivity is improved, but local voltage drops occur causing test failures
Solution Approach 1:
By implementing periodic operation with phased clock signals, the patent distributes the power consumption load over time rather than concentrating it in simultaneous operations. This reduces local voltage drops that would cause test failures, thereby improving test accuracy while maintaining productivity through continued multi-chain operation.
Solution Approach 2:
Segmenting scan chains into groups with different clock phases allows the system to maintain multiple operational chains simultaneously without the harmful effect of concentrated power draw. This segmentation strategy ensures reliable testing by preventing voltage drops below operational thresholds while preserving high productivity.
3Power
If scan chains are staggered to reduce peak power, then power consumption is reduced, but testing complexity increases
Solution Approach 1:
The patent introduces a clock control circuit as an intermediary component that manages the phased clock distribution to multiple scan chain groups. This intermediary handles the complexity of staggered timing control, isolating the complexity from the main testing logic and providing a systematic way to manage power reduction without significantly increasing overall device complexity.
Data Source
AI summary
According to one embodiment, a semiconductor device includes: a first scan chain and a second scan chain each including a plurality of cascaded flip-flops; a plurality of power supply lines that supply a power supply voltage to the first and second scan chains, extend in a first direction, and are arranged in a second direction intersecting with the first direction; and a clock control circuit that supplies a first clock to the first scan chain and a second clock to the second scan chain, the second clock having timing different to that of the first clock. The plurality of flip-flops are arranged along the second direction.