Multi-Capture Scan Test Using Staggered Clock Pulses
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Solution Overview
Problem
Current scan testing methods for integrated circuits with multiple clock domains face challenges in reducing test time while maintaining fault coverage and detecting inter-clock-domain faults, particularly in at-speed scan tests, due to the complexity of synchronizing capture clock pulses across domains.
Innovation Solution
The implementation of a staggered capture clock pulse generation method using on-chip clock control devices, which generate capture clock pulses based on a common slow clock signal, allowing for controlled delay and synchronization of pulses across multiple clock domains without requiring cross-domain triggering, thereby enabling efficient testing of multiple domains simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If capture clock pulses are applied simultaneously to multiple clock domains, then test time is reduced, but test coverage is lost due to unknown values in data propagation across clock domains
Solution Approach 1:
The patent applies periodic action by using a slow clock signal to periodically trigger capture pulses in different clock domains in sequence. The slow clock generates periodic trigger signals that activate capture operations in each clock domain at different time intervals, ensuring proper timing for cross-domain signal propagation while maintaining reduced test time compared to traditional sequential methods.
Solution Approach 2:
The patent introduces an intermediary slow clock signal that mediates between the fast system clock and the capture operations in multiple clock domains. This slow clock acts as a coordinator that sequences the capture pulses across domains, ensuring that data has sufficient time to propagate across clock domain boundaries while maintaining synchronized control of the entire test process.
2Reliability
If capture clock pulses are applied in sequence to multiple clock domains, then test coverage is maintained, but test time increases significantly
Solution Approach 1:
The patent uses periodic action by implementing a slow clock that generates periodic trigger signals to activate capture operations in different clock domains. This periodic triggering allows multiple domains to be tested in a coordinated sequence rather than traditional serial testing, reducing overall test time while maintaining proper timing for cross-domain signal propagation.
Solution Approach 2:
The patent applies continuity of useful action by overlapping capture operations across different clock domains within the same test cycle. Instead of completing all captures in one domain before moving to the next, the slow clock enables continuous capture operations to proceed across multiple domains in an optimized sequence, eliminating idle time and maintaining continuous testing throughput.
3Ease of manufacture
If traditional sequential testing of clock domains is used, then cross-domain faults cannot be detected, but test pattern generation remains simple
Solution Approach 1:
The patent applies universality by designing a single slow clock mechanism that serves multiple functions: it triggers capture operations in all clock domains, sequences the timing of captures across domains, and enables both intra-domain and inter-domain fault detection. This universal controller replaces the need for separate complex control logic for each domain while enabling cross-domain testing capabilities.
Solution Approach 2:
The slow clock signal serves as an intermediary that enables cross-domain fault detection without requiring complex cross-domain triggering logic. It mediates the timing and coordination between different clock domains, allowing simple test pattern generation while simultaneously enabling the detection of inter-clock-domain faults through properly sequenced capture operations.
4Speed
If fast system clock is used for scan testing, then testing speed increases, but power dissipation increases significantly
Solution Approach 1:
The patent uses periodic action by employing a slow clock signal with lower frequency than the system clock to trigger capture operations. This periodic triggering at reduced frequency maintains the ability to perform at-speed capture (using the fast system clock for actual data capture) while significantly reducing the power consumption associated with the test clock signal generation and distribution.
Solution Approach 2:
The patent applies parameter changes by separating the timing control function (performed by the slow clock with optimized frequency) from the data capture function (performed by the fast system clock). This parameter separation allows the test system to operate at high speed for actual testing while using a lower-frequency control signal that consumes less power, optimizing both speed and power consumption.
Data Source
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AI summary
A circuit comprises a plurality of clock control devices. Each of the clock control devices is configured to generate a scan test clock signal for a particular clock domain in the circuit and comprises circuitry configured to select clock pulses of a fast clock signal as scan capture clock pulses for the particular clock domain based on a particular clock pulse of a slow clock signal and a scan enable signal. The order and spacing between the groups of the scan capture clock pulses for different clock domains correspond to the order and spacing of the clock pulses of the slow clock signal.