Staggered Scan Clocking in IC Test Mode to Cut Peak Power
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Solution Overview
Problem
Integrated circuits face high power consumption during scan-based testing, leading to thermal issues and potential structural damage, especially in low-power designs, where peak and average power exceed circuit limits, affecting reliability and performance.
Innovation Solution
The integration of clock staggering test circuitry generates staggered shift and capture clock signals, reducing peak power by operating at a frequency divided by M, where M is greater than or equal to the number of functional logic blocks, and ensuring non-overlapping clock signals to manage power consumption without increasing test time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan-based testing is used to achieve comprehensive fault coverage, then test coverage is improved, but power consumption increases significantly
Solution Approach 1:
The circuit is divided into multiple functional blocks (first functional block, second functional block, etc.), each with its own dedicated scan chains and clock signals. This segmentation allows independent control of power consumption in different blocks during testing, enabling comprehensive test coverage while managing overall power consumption through selective activation.
Solution Approach 2:
Different functional blocks are assigned different clock signals (first clock signal, second clock signal) that can be independently controlled. This local quality approach allows each block to be tested with appropriate clocking while preventing simultaneous switching of all blocks, thereby reducing peak power consumption while maintaining test coverage.
2Productivity
If all clocks are applied simultaneously during shift mode to maximize testing efficiency, then productivity is improved, but peak power consumption increases
Solution Approach 1:
Different functional blocks are tested in periodic sequences using staggered clock signals. The first clock signal and second clock signal are applied at different times rather than simultaneously, creating a periodic testing pattern that maintains productivity while reducing peak power consumption by avoiding simultaneous switching of all scan chains.
3Measurement precision
If test patterns switch as many nodes as possible to improve test coverage, then measurement precision is improved, but thermal load increases
Solution Approach 1:
The circuit is divided into multiple functional blocks with dedicated scan chains, allowing test patterns to activate nodes in different blocks at different times. This segmentation enables comprehensive node coverage while distributing thermal load across time, preventing simultaneous high-power switching that would cause excessive thermal accumulation.
Solution Approach 2:
Test patterns are applied in periodic sequences to different functional blocks using staggered clock signals. This periodic action ensures that all nodes are eventually tested for comprehensive coverage while spreading the thermal load over time, preventing peak thermal conditions that would occur with simultaneous full-circuit activation.
4Ease of operation
If the complete clock network toggles simultaneously during shift mode to maintain transparency, then ease of operation is maintained, but power consumption increases
Solution Approach 1:
Different segments of the clock network are controlled independently with separate clock signals (first clock signal, second clock signal). This local quality approach maintains the transparency and ease of operation of the clock network in each functional block while preventing simultaneous toggling of the complete clock network, thereby reducing overall power consumption.
Data Source
AI summary
An integrated circuit includes an N number of functional logic blocks, with N being greater than or equal to two, and clock staggering test circuitry. When the clock staggering test circuitry is in a shift mode, N staggered shift clock signals are generated for respective ones of the N functional logic blocks. Each of the N staggered shift clock signals has a frequency equal to a frequency of an external test clock signal divided by M, where M is greater than or equal to N. The peak power of the integrated circuit is reduced during the shift mode as a result of the staggered shift clock signals.