Staggered Scan Shift Clock Distribution for Peak Power Reduction
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Solution Overview
Problem
Scan shift operations in integrated circuit testing face challenges with high peak power issues due to high toggling rates and logic activity, leading to voltage drops and potential chip failures, necessitating slower clock speeds to avoid power-related problems.
Innovation Solution
The system reduces peak power by staggering the test clock to CPU Cores and cache during the scan shift cycle, using multiplexing and delay elements to distribute clock signals, allowing higher clock speeds while minimizing voltage drops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scan shift operations are run at higher clock speeds to reduce test time, then productivity is improved, but peak power consumption increases causing voltage drops and potential chip failures
Solution Approach 1:
The patent segments the simultaneous switching of all flip-flops into multiple time-phased groups. By dividing the scan shift operation into sequential phases where different subsets of flip-flops switch at different times, the peak current demand is divided into smaller, manageable segments that occur over time rather than all at once, thereby reducing peak power consumption while maintaining high clock speeds
Solution Approach 2:
The patent implements periodic action by using phased clocking sequences where flip-flops are activated in repeating cycles rather than simultaneously. This periodic activation pattern ensures that power consumption is distributed over time intervals, preventing sustained peak power conditions while allowing the overall test operation to proceed at high speed
2Speed
If all flip-flops switch simultaneously during scan shift to enable high-speed operation, then speed is improved, but voltage drop from power rails increases causing malfunction
Solution Approach 1:
The patent segments the flip-flop switching into multiple time-phased groups, where each group switches at a slightly different time determined by phase shift values. This temporal segmentation reduces the simultaneous current draw from power rails, thereby minimizing voltage drops and maintaining voltage stability within acceptable ranges while preserving high clock speeds
Solution Approach 2:
The patent changes the timing parameters of clock signals by applying different phase shift values to different scan chains or flip-flop groups. By adjusting these temporal parameters, the system distributes the switching activity over time, reducing peak current demand and preventing excessive voltage drops that would compromise reliability
3Productivity
If high toggling rates are used during scan shift to reduce test time, then productivity is improved, but dynamic power consumption increases causing excessive heat dissipation
Solution Approach 1:
The patent implements periodic action by cycling through different phases of flip-flop activation in a repeating sequence. This periodic pattern ensures that not all flip-flops are toggling at maximum rate simultaneously, distributing the energy consumption over time intervals and reducing peak heat generation while maintaining high overall test speed
Solution Approach 2:
The patent segments the high-speed toggling activity into time-phased groups, where each group operates at high speed but in sequence rather than parallel. This segmentation maintains the high toggling rates needed for fast testing while distributing the thermal load across different time periods, preventing excessive heat dissipation
Data Source
AI summary
A method for reducing peak power during a scan shift cycle is presented. The method comprises multiplexing a test clock with a functional clock on a integrated circuit at the root of a clock tree. The method also comprises adding a plurality of delay elements on a clock path, wherein the clock path is a signal resulting from the multiplexing. Further, the method comprises routing the clock path to a plurality of cores and a cache, e.g., an L2C cache, on the integrated circuit. Finally the method comprises staggering the test clock received by each of the plurality of cores and the cache by employing the delay elements during a scan shift cycle.