Staggered Scan Thresholds for Memory Error Mitigation

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Solution Overview

Problem

Memory systems, such as solid-state drives, face performance bottlenecks due to simultaneous triggering of scan and fold events across multiple groups of memory cells, leading to increased error handling overhead and reduced system performance under read-intensive workloads.

Innovation Solution

Adjusting and staggering scan event thresholds for different groups of memory cells to distribute scan and fold events in time, thereby reducing the number of simultaneous events and minimizing performance impact.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If scan and fold events are triggered simultaneously across multiple groups of memory cells, then error detection and correction are performed, but system performance deteriorates due to increased error handling overhead

Engineering Contradiction:
Improveerror detection and correctionVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The memory device is divided into multiple groups of memory cells, each with its own scan event threshold. This segmentation allows independent control of scan events for different groups, enabling the system to distribute error detection operations across time rather than executing them simultaneously, thereby reducing performance impact while maintaining comprehensive error detection.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different scan event thresholds are pre-configured for different groups of memory cells based on their respective error characteristics and usage patterns. This preliminary configuration enables the controller to proactively distribute scan events in time, preventing simultaneous error handling operations that would degrade system performance.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If scan event thresholds are uniform across all memory cell groups, then implementation is simple, but performance bottlenecks occur during read-intensive workloads

Engineering Contradiction:
Improveimplementation simplicityVSAvoidperformance under read-intensive workloads
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

Instead of using a uniform scan event threshold for all memory cell groups, the system implements group-specific thresholds tailored to local characteristics. Each group's threshold is adjusted based on its error rate, usage pattern, and operational characteristics, allowing optimized error detection timing that prevents performance bottlenecks during read-intensive workloads while maintaining manageable implementation complexity.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11709633B2Adjusting scan event thresholds to mitigate memory errors
Publication Date: 2023.07.25 MICRON TECHNOLOGY INC
  • US11709633B2 patent drawing
  • US11709633B2 patent drawing
  • US11709633B2 patent drawing

AI summary

Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.