Staggered Self-Refresh Timing in Memory Dies
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Solution Overview
Problem
Concurrent self-refreshing of multiple memory dies in memory devices leads to power spikes, straining the power delivery network and causing interference between memory cells, resulting in inefficiencies and potential voltage droops.
Innovation Solution
Introducing a staggered or asynchronous timing for refresh operations in memory dies by modifying the timing of signaling for internal refresh operations using fuse arrays to delay refresh operations, allowing each memory die to perform refreshes independently and reducing concurrent power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory dies perform self-refreshing concurrently, then refresh operations are completed efficiently, but power spikes occur and cause voltage droops and interference between memory cells
Solution Approach 1:
The patent implements periodic refresh operations with staggered timing for different memory dies. Each memory die performs refresh operations at different time intervals within the self-refresh mode, distributing the periodic refresh actions across time to avoid simultaneous power consumption peaks while maintaining data integrity in all memory banks.
Solution Approach 2:
The patent segments the refresh operations across multiple memory dies by assigning different refresh timing to each die. The memory device is divided into multiple independent refresh cycles, where each memory die operates autonomously with its own timing offset, thereby segmenting the overall power consumption profile and eliminating concurrent peaks.
2Reliability
If multiple memory dies perform self-refreshing concurrently, then refresh coverage is maximized, but interference between memory cells occurs due to simultaneous current draw
Solution Approach 1:
The patent employs periodic refresh operations with staggered phases for different memory dies. Each die performs its refresh cycle at a different phase offset, ensuring that all memory banks receive timely refresh attention while the periodic distribution of operations prevents simultaneous current draw that would cause interference between adjacent memory cells.
Solution Approach 2:
The patent implements preliminary timing offsets for refresh operations in each memory die before actual refresh begins. By pre-staggering the start times of refresh operations across different dies, the system ensures that refresh coverage is maintained while the preliminary timing distribution prevents harmful simultaneous current draw and interference between memory cells.
3Device complexity
If uniform timing is used for refresh operations across all memory dies, then control is simplified, but power delivery network is strained due to simultaneous current draw
Solution Approach 1:
The patent implements periodic refresh operations with automatically staggered timing for each memory die. The control logic generates periodic refresh signals with built-in time offsets for different dies, maintaining relatively simple control architecture while the periodic staggering inherently distributes power consumption and reduces stress on the power delivery network.
Data Source
AI summary
First signaling indicative of instructions to enter a self-refresh (SREF) mode can be received concurrently by a plurality of memory dies. Responsive to a memory die of the plurality of memory dies entering the SREF mode, self-refreshing of memory banks of the memory die can be delayed, at the memory die and based on fuse states of an array of fuses of the memory die, an amount of time relative to receipt of the signaling by the memory die. Delaying self-refreshing of memory banks of memory dies in a staggered, or asynchronous, manner can evenly distribute power consumption of the memory dies so that the likelihood of an associated power spike is reduced or eliminated.