Staggered Semiconductor Boundary Contacts for Chip Area Reduction
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Solution Overview
Problem
The arrangement of substrate bias contacts between P-type and N-type semiconductor regions in semiconductor devices requires a significant increase in chip area and manufacturing cost due to the need for a wide space between transistors to accommodate these contacts.
Innovation Solution
The semiconductor device design features a staggered arrangement of N-well and P-well contacts along the boundary between the semiconductor regions, with the contacts alternating in a direction perpendicular to their arrangement, allowing for a reduced width of the boundary portion and thus minimizing the chip area and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If substrate bias contacts are arranged in the boundary portion between P-type and N-type semiconductor regions, then substrate bias potential can be applied to transistors, but the width of space between transistors must be increased to accommodate the contacts
Solution Approach 1:
The patent applies staggered arrangement in the perpendicular direction (dimension) to separate the contact locations of first and second conductivity type regions. Instead of arranging contacts at the same boundary position, the first contacts are offset from the second contacts in the direction perpendicular to the boundary, allowing both contact types to share the boundary portion without requiring increased transistor spacing.
2Reliability
If a sufficient number of substrate bias contacts are arranged for each semiconductor region, then sufficient substrate bias potential is applied to all transistors, but the chip area and manufacturing cost increase
Solution Approach 1:
The patent merges the contact arrangements of P-type and N-type regions by using a shared boundary portion. The staggered arrangement allows both first contacts (for P-type) and second contacts (for N-type) to be integrated along the same boundary, reducing the total number of contacts needed compared to separate arrangements, thereby lowering manufacturing complexity and cost.
Data Source
AI summary
A device includes first and second semiconductor-regions located in a substrate which are adjacent to each other at a boundary. First contacts are located in the first semiconductor-region along the boundary and are electrically connected to the first semiconductor-region. Second contacts are located in the second semiconductor-region along the boundary and are electrically connected to the second semiconductor-region. The second contacts are not located in parts of the second semiconductor-region on an opposite side to the first contacts across the boundary. The parts of the second semiconductor-region are adjacent to the first contacts in a first direction s perpendicular to an arranging direction of the first and second contacts. The first contacts are not located in parts of the first semiconductor-region on an opposite side to the second contacts across the boundary. The parts of the first semiconductor-region are adjacent to second contacts in the first direction.