Staggered Semiconductor Chip Pad Power Supply IR Drop
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Solution Overview
Problem
In semiconductor chips with external connection pads arranged in three or more rows, the increased resistance of power supply lines due to larger distances and reduced I/O cell widths leads to potential circuit misoperation from IR drops, and attempts to reduce this resistance result in increased chip area.
Innovation Solution
The use of external connection pads in a staggered configuration, where the first pad in the outermost row is connected to subsequent pads in the same layer, reduces the resistance of power supply lines to the internal core circuit, preventing IR drops without increasing chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If external connection pads are arranged in three or more rows in a staggered configuration, then the chip area is increased, but the resistance of power supply lines increases causing IR drops and circuit misoperation
Solution Approach 1:
The patent applies dimensionality change by transitioning from a two-row staggered configuration to a three-row staggered configuration of external connection pads. This spatial rearrangement in multiple dimensions allows optimization of both chip area utilization and power supply line resistance, resolving the contradiction between increased chip area and power supply stability.
2Quantity of substance
If the distance from chip end to internal core region is increased to accommodate more pad rows, then more pads can be arranged, but the power supply line resistance increases
Solution Approach 1:
The patent applies segmentation by dividing the external connection pads into three separate rows rather than using a single row or two-row configuration. This segmentation allows for optimized spacing and reduced power supply line resistance while accommodating a larger number of pads, thus resolving the contradiction between pad quantity and power supply stability.
3Quantity of substance
If I/O cell width is reduced to accommodate more pads, then the number of pads increases, but the power supply line resistance in each I/O cell increases
Solution Approach 1:
The patent applies dimensionality change by arranging pads in a three-row staggered configuration, which optimizes the spatial distribution of pads and I/O cells. This multi-dimensional arrangement allows for reduced I/O cell width while maintaining acceptable power supply line lengths, resolving the contradiction between pad quantity and power supply line length.
Data Source
AI summary
In a semiconductor chip in which external connection pads are arranged in three or more rows in a staggered configuration at the peripheral portion thereof, a first pad which is arranged in the outermost row is used as a power supply pad or a ground pad for an internal core circuit. To the first pad, a second pad which is arranged in the second outermost row is connected with a metal in the same layer as a pad metal. The resistance of a power supply line to the internal core circuit has a value of the parallel resistance of a resistance from the first pad and a resistance from the second pad, which is by far lower than the resistance from the first pad. Therefore, it is possible to prevent circuit misoperation resulting from an IR drop in the power supply of the internal core circuit.