Staggered Semiconductor Test Timing Reduces Peak Power
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Solution Overview
Problem
The testing of semiconductor devices often results in peak noise and peak power consumption, which degrades test performance in production environments, especially when multiple devices are tested simultaneously, leading to inefficiencies and potential damage.
Innovation Solution
A test device and method that utilize delay control circuits to stagger the timing of test inputs to semiconductor devices, allowing each device to perform tests at different times, thereby reducing peak noise and power consumption by dispersing the testing load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor devices are tested simultaneously in parallel, then test productivity is improved, but peak noise and peak power consumption increase excessively
Solution Approach 1:
The patent applies periodic action by implementing a test scheduling mechanism that distributes test operations across different time periods. The test controller assigns different time slots to different device groups, creating a periodic testing pattern that maintains high productivity while preventing simultaneous peak loads. This temporal distribution ensures that testing continues systematically without overwhelming noise or power consumption spikes.
Solution Approach 2:
The patent implements dynamics by making the test scheduling adaptive and flexible. The test controller dynamically adjusts the timing and grouping of device tests based on real-time conditions, allowing the system to optimize between productivity and noise/power management. This dynamic scheduling enables the system to respond to varying test requirements while maintaining control over peak conditions.
2Adaptability or versatility
If operating current is increased to test high-capacity memory devices, then test capability for multi-channel devices is improved, but peak noise and peak power consumption become excessive
Solution Approach 1:
The patent applies segmentation by dividing the multi-channel memory devices into separate test groups or subsets. Instead of testing all channels of all devices simultaneously at high current, the system segments the testing into manageable portions across different time slots. This segmentation allows high-capacity devices to be tested effectively while distributing the current load to avoid excessive peak noise and power consumption.
Solution Approach 2:
The patent uses periodic action to cycle through different device groups and channel configurations. By implementing periodic testing sequences where different subsets of channels are activated in alternating time periods, the system maintains the capability to test multi-channel high-capacity devices while preventing sustained peak current conditions that would generate excessive noise and power consumption.
3Speed
If test inputs are provided in parallel to all devices, then test speed is maintained, but peak power consumption and noise degradation occur
Solution Approach 1:
The patent implements dynamics by creating a flexible, adaptive test scheduling system that adjusts the parallelism level dynamically. Rather than maintaining fixed parallel testing for all devices, the system dynamically determines which devices can be tested in parallel at any given time based on current load conditions. This dynamic approach preserves test speed where possible while preventing peak power consumption and noise degradation when devices are tested in controlled sequences.
Data Source
AI summary
A test device includes a test mounting circuit having a plurality of semiconductor devices mounted thereon as respective devices-under-test. Each device-under-test includes a corresponding delay control circuit and a target circuit therein. Test logic is provided, which is electrically coupled to the test mounting circuit. The test logic is configured to generate a test input(s), which is provided in parallel to the delay control circuits within the plurality of devices-under-test. The delay control circuits include at least first and second delay control circuits, which are configured to pass the test input(s) to corresponding first and second target circuits during respective first and second test time intervals that are out-of-phase relative to each other in order to achieve more uniform power consumption requirements of the test mounting circuit during testing.