Staggered Sense Amplifier Grouping for Peak Current Reduction
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Solution Overview
Problem
Destructive readout semiconductor memory devices, such as DRAMs, face challenges in managing peak current consumption during data readout and writeback operations, leading to voltage drops and power supply noise, as simultaneous operation of sense amplifiers results in concurrent bit line charging and readout currents.
Innovation Solution
Implementing a timing control mechanism that disables sense amplifiers while switch circuits are on, then enables them and turns on switch circuits in groups at staggered intervals to prevent concurrent bit line charging, thereby dispersing peak currents and reducing overall peak current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If sense amplifiers are enabled simultaneously to read out data from multiple memory cells, then data readout speed is improved, but peak current consumption increases due to concurrent bit line charging
Solution Approach 1:
The sense amplifiers are divided into multiple groups, and bit line charging is performed in a staged manner where different groups of sense amplifiers are enabled at different time intervals. This segmentation of the simultaneous operation into sequential groups reduces the peak current consumption while maintaining overall data readout speed.
Solution Approach 2:
The patent employs periodic enabling of sense amplifier groups with staggered timing. Instead of all sense amplifiers being enabled at once, they are enabled in periodic waves with different delays, which distributes the current consumption over time while maintaining continuous data readout operation.
2Productivity
If multiple sense amplifiers operate at the same time to read concurrent bits, then productivity is improved, but voltage drop and power supply noise increase due to current concentration
Solution Approach 1:
Sense amplifiers are segmented into multiple groups that operate with staggered timing. This allows concurrent bit reading to continue with high productivity while the segmented operation prevents current concentration that causes voltage drop and power supply noise.
Solution Approach 2:
The patent applies preliminary timing delays to different groups of sense amplifiers before they are enabled. This preliminary action of staggering the enable timing prevents simultaneous current draw from multiple sense amplifiers, thereby reducing voltage drop and power supply noise while maintaining overall reading productivity.
Data Source
AI summary
Provided is a destructive readout semiconductor memory device capable of avoiding concentration of a writeback current, in which a switch circuit (24) is provided between each bit line (21) and each sense amplifier (26). In writeback, the switch circuits are turned on at staggered time points. In readout, the switch circuits are turned on to read memory cell data to the sense amplifiers while the sense amplifiers are turned off, and the switch circuits are then turned off once. After that, the sense amplifiers are turned on to amplify the read data. The switch circuits are subsequently divided into groups and turned on again to write back the data amplified by the sense amplifiers to the memory cells. The switch circuits are divided into groups to be turned on at staggered time points during the writeback, to thereby avoid concentration of the writeback current in one time period.