Staggered Silicon Pillar Layout for Nonvolatile Memory Cell Area Reduction
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Solution Overview
Problem
Current three-dimensionally structured nonvolatile semiconductor memory devices face limitations in achieving higher integration density due to the arrangement of silicon pillars and select gate electrodes, which restricts further miniaturization and increases cell area.
Innovation Solution
The proposed solution involves a staggered layout of silicon pillars penetrating through select gate electrodes, with neighboring pillars penetrating through different positions in the width direction of the gate electrodes, allowing for a reduction in the smallest feature size and cell area while maintaining the shortest distance between pillars to avoid interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If silicon pillars are arranged in a conventional grid pattern penetrating through select gate electrodes, then the device structure is simple to manufacture, but the cell area and smallest feature size cannot be reduced further
Solution Approach 1:
The patent applies asymmetry by offsetting the positions of silicon pillars in alternating rows relative to the select gate electrodes. Instead of symmetric alignment where all pillars penetrate at the same position, pillars in even rows are shifted by a predetermined distance compared to pillars in odd rows. This asymmetric arrangement reduces the cell area while maintaining manufacturability through standard lithography processes.
Solution Approach 2:
The patent introduces dimensional change by arranging silicon pillars not only in the vertical stacking direction but also with lateral offset in the planar direction. The pillars are positioned at different locations in the width direction of select gate electrodes for alternating rows, effectively utilizing both vertical and lateral dimensions to reduce the footprint and cell area.
2Quantity of substance
If the number of stacked films is increased to achieve higher integration density, then the storage capacity increases, but the number of lithography steps and manufacturing complexity increase
Solution Approach 1:
The patent applies universality by designing a unified multilayer structure where select gate electrodes serve multiple functions: they act as control gates for memory cells, provide structural support for stacked films, and enable the asymmetric pillar arrangement. This multi-functional design allows increased integration density through film stacking without proportionally increasing lithography steps, as the same electrode patterns serve multiple purposes.
3Area of stationary object
If silicon pillars are positioned closer together to reduce cell area, then integration density increases, but interference between neighboring pillars occurs
Solution Approach 1:
The patent applies local quality by creating different spatial relationships for different groups of pillars. Pillars in the same row maintain uniform spacing, while pillars in alternating rows are offset by a predetermined distance. This localized variation in positioning optimizes the distance between neighboring pillars to prevent interference while minimizing cell area. The offset distance is specifically designed to maintain reliable operation while achieving higher density.
Data Source
AI summary
A nonvolatile semiconductor memory device includes: a multilayer body with a plurality of insulating films and electrode films alternately stacked therein; a plurality of select gate electrodes provided on the multilayer body, extending in one direction orthogonal to a stacking direction of the multilayer body, and spaced from each other; semiconductor pillars penetrating through the multilayer body and the select gate electrodes; and a charge storage film provided between one of the electrode films and one of the semiconductor pillars, two neighboring ones of the semiconductor pillars penetrating through a common one of the select gate electrodes and penetrating through mutually different positions in a width direction of the select gate electrodes.