Staggered Stacked Circuits for Increased Nanosheet Effective Width
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Solution Overview
Problem
The challenge in semiconductor fabrication is to increase the effective width of circuits while maintaining efficiency and reducing costs, as the industry scales down to smaller geometries, increasing complexity and requiring advancements in manufacturing techniques.
Innovation Solution
The solution involves constructing semiconductor structures with staggered stacked circuits, where the first logic cell uses narrow nanosheet devices and the second logic cell uses wider nanosheet devices, allowing for increased effective width without area penalty, and implementing a method that includes forming dielectric isolation layers, constructing nanosheet devices with narrow and wide sheets, and forming back-end-of-line components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If narrow nanosheet devices are used in logic cells, then area efficiency is improved, but effective width is limited
Solution Approach 1:
The patent transitions from planar device layout to vertical stacking, arranging nanosheet devices in multiple tiers along the vertical dimension. This allows the second logic cell to stack nanosheets above the first logic cell, effectively multiplying the effective width without increasing the lateral footprint, thereby resolving the contradiction between area efficiency and effective width.
Solution Approach 2:
The patent implements a nested configuration where the second logic cell's nanosheet devices are positioned vertically above and overlapping with the first logic cell's nanosheet devices. This nesting arrangement allows both logic cells to share the same lateral space while maintaining distinct effective widths, achieving high effective width multiplication within a compact area.
2Productivity
If geometry size is scaled down, then production efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the semiconductor structure into discrete logic cells (first logic cell, second logic cell) with distinct nanosheet devices, each independently formed with controlled effective widths. This segmentation allows modular manufacturing where each logic cell can be processed separately through the fabrication steps, managing complexity while maintaining high production efficiency through standardized processes.
Data Source
AI summary
A semiconductor structure including a first logic cell having a first plurality of nanosheet devices along an axis and a second logic cell having a second plurality of nanosheet devices along the axis. Nanosheets of the second plurality of nanosheet devices are wider than nanosheets of the first plurality of nanosheet devices. The first logic cell is a same type as the second logic cell. The first and second logic cells can include inverter circuits or NAND circuits or NOR circuits. When the first logic cell has a height X, a width Y, and an effective width (Weff) Z, then the second logic cell has a height 2X, a width Y, and Weff>2.5 Z.