Staggered Strapping Contacts for Non-Volatile Memory Process Margin
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Solution Overview
Problem
The existing non-volatile memory cell arrays face reduced process margin due to the close proximity of strapping contacts, leading to decreased yield as the memory cells are scaled down, as the contacts are located at the same column position, reducing the minimum separation and increasing the risk of process deviation.
Innovation Solution
The strapping of coupling gates is improved by staggering the contact locations, such that they are not in the same column, increasing the distance between contacts and allowing for a larger process margin, while maintaining similar strapping efficiency by adjusting the periodicity to every 256 columns, which allows for greater room for error as the memory cells are scaled.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If contacts are located at the same column position for strapping coupling gates, then strapping efficiency is improved, but process margin is reduced and manufacturing precision deteriorates
Solution Approach 1:
The patent applies dimensionality change by transitioning from a single-column contact arrangement to a multi-column staggered contact arrangement. Specifically, contacts are distributed across multiple columns (e.g., columns 0, 128, 256, 384) rather than being concentrated in one column, thereby increasing the minimum separation distance between contacts while maintaining strapping coverage efficiency.
2Area of moving object
If memory cells are scaled down, then device density is improved, but process margin is reduced due to closer contact proximity
Solution Approach 1:
The patent applies segmentation by dividing the contact arrangement into multiple segments distributed across different columns. Instead of having all contacts in one location, the strapping contacts are segmented and placed at staggered positions (columns 0, 128, 256, 384), which increases the minimum separation between adjacent contacts and provides greater process margin for scaled-down memory cells.
Data Source
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Figure 3
AI summary
The present invention an array of non-volatile memory cells has a semiconductor substrate of a first conductivity type with a top surface. A plurality of spaced apart first regions of a second conductivity type are in the substrate along the top surface. Each first region extends in a row direction. A plurality of spaced apart second regions of the second conductivity type are in the substrate along the top surface. Each second region is spaced apart from an associated first region in a column direction, perpendicular to the row direction. A channel region is defined between each second region and its associated first region in the column direction. Each channel region has a first portion and a second portion. A plurality of spaced apart word line gates extend in the row direction. Each word line gate is positioned over and is insulated from the first portion of a channel region.