Staggered Stud Bumps for Semiconductor Package Pitch Reduction
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Solution Overview
Problem
The existing semiconductor structures face challenges in reducing the pitch of conductive layers due to manufacturing constraints, limiting the increase in I/O numbers as the minimum width of conductive pillars is around 20 μm, resulting in larger chip sizes and reduced connectivity efficiency.
Innovation Solution
The semiconductor package device incorporates staggered conductive bumps with specific shapes and arrangements, allowing for reduced pitch between conductive layers by overlapping the bumps in a direction perpendicular to the circuit layers, with the width of the widest portion of the bumps being greater than the conductive layers, and using a shape defined by the equation d < D - 2(t/tanθ), where d is the interface width, D is the bottom surface width, t is the distance between the interface and the bottom surface, and θ is the angle defined by the bottom surface and the edge of the widest portion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the minimum width of conductive pillar is maintained at around 20 μm due to manufacturing constraints, then the manufacturing precision is maintained, but the pitch of conductive layer cannot be reduced further, limiting the increase in I/O numbers
Solution Approach 1:
The patent introduces a vertical dimension to the conductive pillar structure by forming a tapered shape with a wider bottom surface than top surface. This dimensional change allows the pillar to span larger horizontal distances while maintaining manufacturing feasibility, effectively reducing the pitch requirement without compromising the minimum width constraint.
Solution Approach 2:
The patent changes the geometric parameters of the conductive pillar by implementing a tapered configuration where the bottom surface width is greater than the top surface width. This parameter modification enables the structure to achieve both manufacturing precision and reduced pitch, thereby increasing I/O density.
2Productivity
If the pitch of conductive layer is reduced to accommodate more I/O numbers, then the I/O numbers increase, but the manufacturing constraints cannot be satisfied
Solution Approach 1:
By adding vertical tapering to the conductive pillar structure, the invention enables reduced horizontal pitch while maintaining manufacturability. The tapered geometry provides the necessary structural integrity across smaller pitch dimensions that would otherwise be difficult to manufacture.
Solution Approach 2:
The patent employs a composite structure combining conductive material with a tapered geometric configuration. This composite approach integrates both the electrical conductivity function and the mechanical stability requirement, allowing reduced pitch while satisfying manufacturing constraints.
3Strength
If the width of conductive pillar is increased to maintain strong electrical connections, then the electrical connection strength is maintained, but the chip size increases
Solution Approach 1:
The tapered geometry introduces a vertical dimension that allows the conductive pillar to achieve both strong electrical connections and compact horizontal footprint. The wider bottom surface provides structural strength while the narrower top surface reduces the required chip area.
Solution Approach 2:
By changing the width parameter along the vertical axis of the conductive pillar, the invention creates a tapered structure that optimizes both electrical connection strength and chip area utilization. The variable width parameter enables simultaneous achievement of mechanical strength and space efficiency.
Data Source
AI summary
A semiconductor package device is provided that includes a first circuit layer having a first conductive layer and a first stud bump and a second circuit layer having a second conductive layer and a second stud bump. The first stud bump has a first portion and a second portion, and the second portion of the first stud bump is electrically connected to the second conductive layer. The second stud bump has a first portion and a second portion, and the second portion of the second stud bump is electrically connected to the first conductive layer. The first stud bump partially overlaps the second stud bump in a direction substantially perpendicular to the first circuit layer.