Staggered Sub-Transistor Circuit Block for Crack Resilience
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Solution Overview
Problem
In electronic devices, when a chip cracks, it often leads to complete disability of the circuit block due to signal or voltage transmission issues.
Innovation Solution
The chip design includes a circuit block with first and second transistors divided into sub-transistors connected in parallel, disposed in a staggered manner across different signal lines, ensuring that input signals and voltage are received through different lines, thereby preventing complete disability even if a crack occurs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors are disposed in a single row and receive signals through single signal lines, then the circuit block structure is simple, but a crack on the signal line causes complete disability of the circuit block
Solution Approach 1:
The transistors are divided into multiple sub-transistors connected in parallel within each transistor unit. This segmentation ensures that if one sub-transistor or its signal line is damaged, other sub-transistors can still receive signals through alternative paths, preventing complete circuit block disability while maintaining a relatively simple overall structure.
2Reliability
If transistors are arranged in a staggered manner across multiple rows with different signal lines, then the circuit block is protected against complete disability from cracks, but the device structure becomes more complex
Solution Approach 1:
Transistors are arranged in a staggered pattern across multiple rows, utilizing the spatial dimension to create redundant signal paths. This dimensional arrangement allows signals to reach transistors through multiple routes, ensuring that a crack in one signal line does not disable the entire circuit block, while the staggered layout optimizes space utilization.
3Reliability
If all transistors receive signals through the same signal lines, then the signal distribution is simple, but a crack on the signal line causes complete disability of the circuit block
Solution Approach 1:
Different regions of the circuit block are configured with different signal line connections. Transistors in different rows receive signals through different signal lines, creating local variations in the signal distribution network. This local quality differentiation ensures that a crack in one signal line affects only a portion of the circuit block rather than the entire system.
Data Source
AI summary
A chip is provided. The chip is provided with a circuit block. The circuit block includes a first transistor and a second transistor. The first transistor is divided into a plurality of first sub-transistors connected in parallel. The second transistor is divided into a plurality of second sub-transistors connected in parallel. The first sub-transistors and the second sub-transistors are disposed in a first row and a second row of the circuit block in a staggered manner. The first transistors disposed in the first row and the second row respectively receive a first input signal through different signal lines. The second transistors disposed in the first row and the second row respectively receive a second input signal through different signal lines.