Staggered Switching Control for Parallel Power Semiconductor Load Balancing

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Solution Overview

Problem

Power semiconductor switches connected in parallel in inverters experience unequal loading due to component tolerances and propagation time differences, leading to premature failure and reduced system robustness.

Innovation Solution

A method and control unit that generate individual control signals for power semiconductor switches to stagger their switching times and load distribution, allowing for targeted allocation of switch-on, switch-off, and power line losses, ensuring even loading and optimal utilization of all switches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If power semiconductor switches are connected in parallel to handle higher currents, then the current-carrying capacity is improved, but the loading becomes unequal due to component tolerances and switching time differences, causing individual switches to be overloaded and fail prematurely

Engineering Contradiction:
Improvecurrent-carrying capacityVSAvoidswitch lifespan
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The control device determines individual switching times for each parallel-connected power semiconductor switch in advance, before the actual switching operation. This preliminary timing adjustment compensates for component tolerances and ensures that all switches share the load equally, preventing any single switch from being overloaded and failing prematurely.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If individual switching times are determined for each power semiconductor switch to distribute losses evenly, then the reliability is improved, but the control complexity increases

Engineering Contradiction:
Improvesystem robustnessVSAvoidcontrol complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The control device uses feedback from measured or calculated switching characteristics of each power semiconductor switch to automatically determine appropriate individual switching times. This feedback mechanism allows the system to adapt to component variations without requiring complex manual calibration, thereby improving reliability while keeping control complexity manageable.

Inventive Principle:
Principle #23Feedback

3Loss of energy

If power semiconductor switches are controlled to switch on at different times, then the turn-on and power line losses are distributed more evenly, but the control signal propagation time differences must be compensated

Engineering Contradiction:
Improvepower line lossesVSAvoidsignal propagation compensation
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The control device pre-determines compensation values for signal propagation time differences based on the physical layout and electrical characteristics of the circuit. These compensation values are applied in advance to the control signals sent to each switch, ensuring that all switches receive their effective turn-on command at the intended time, thereby enabling even loss distribution without requiring real-time propagation compensation.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3224950B1Method and device for controlling power semiconductor switches connected in parallel
Publication Date: 2022.02.23 ROBERT BOSCH GMBH
  • EP3224950B1 patent drawingFigure 1
  • EP3224950B1 patent drawingFigure 2~3

AI summary

The invention relates to a method (200) and a control device (1) for controlling at least two power semiconductor switches (LHS1..LHSn) connected in parallel for switching a total current (I_ges). The at least two power semiconductor switches (LHS1..LHSn) connected in parallel each have a gate terminal for controlling the respective power semiconductor switch (LHS1..LHS2). An input terminal (EA) for feeding the total current (I_ges), an output terminal (AA) for discharging the total current (I_ges), and a joint control terminal (S) for receiving a joint control signal (SI) that has the state 'disconnect' or 'connect' are provided. The at least two power semiconductor switches (LHS1..LHSn) connected in parallel are connected to the input terminal (EA) at the input end and to the output terminal (AA) at the output end. At least one ascertainment unit (EE) is designed to receive the joint control signal (SI) at the input end, ascertain at least two individual control signals (SI1..SIn) in accordance with the joint control signal (SI) in order to control the at least two power semiconductor switches (LHS1..LHSn), and output the at least two ascertained individual control signals to the gate terminals of the at least two power semiconductor switches at the output end. The at least two individual control signals (SI1..SIn) each have the state 'disconnect' or 'connect' and differ at least temporarily.