Staggered TFET With SiGe Epitaxy For High Drive Current
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Solution Overview
Problem
Traditional MOSFETs have reached physical limits as device dimensions shrink and operational voltages decrease, necessitating the exploration of alternative transistor types like Tunneling Field Effect Transistors (TFETs) for improved performance in integrated circuits.
Innovation Solution
The development of a staggered-type Tunneling Field Effect Transistor (TFET) fabrication process involving specific doping levels, epitaxial deposition of SiGe drain regions, and the use of high-k gate dielectrics, along with a planarization process, to enhance tunneling behavior and drive current, compatible with current CMOS manufacturing techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional MOSFETs are used with shrinking device dimensions and decreasing operational voltages, then device density and integration are improved, but device performance and reliability deteriorate due to reaching physical limits
Solution Approach 1:
The patent changes the fundamental operating principle of the transistor from traditional MOSFET drift-diffusion transport to tunneling transport by modifying the band structure parameters. This is achieved through the staggered heterostructure design with specific band offsets, enabling quantum mechanical tunneling that overcomes the physical limits of scaled MOSFETs while maintaining high device density
Solution Approach 2:
The patent employs a composite heterostructure combining different semiconductor materials with distinct band structures (e.g., SiGe source/drain regions with Si channel). This composite approach creates favorable band alignment for enhanced tunneling while maintaining CMOS compatibility, resolving the contradiction between high density and reliable performance
2Adaptability or versatility
If conventional TFET structures are used, then alternative transistor operation is achieved, but drive current remains insufficient for commercial applications
Solution Approach 1:
The patent applies local quality by creating a staggered heterostructure where different regions have optimized properties: the SiGe source/drain regions provide heavy doping for high tunneling probability, the Si channel provides appropriate effective mass, and the gate dielectric provides strong field control. This localized optimization in each region collectively enhances drive current while maintaining TFET operation
Solution Approach 2:
The patent introduces a staggered offset configuration in the vertical dimension, where the gate electrode extends beyond the channel region on one side. This dimensional change creates an additional tunneling path and enhances gate control over the tunneling barrier, significantly improving drive current beyond conventional planar TFET structures
3Power
If staggered-type TFET fabrication process is implemented with epitaxial deposition and high-k gate dielectrics, then tunneling behavior and drive current are enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary action by performing selective epitaxial deposition of SiGe regions before complete trench formation, and by preparing high-k gate dielectric layers in advance. These preliminary steps establish the staggered heterostructure and tunneling regions before final device assembly, making the complex fabrication process more manageable and compatible with existing CMOS workflows
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a TFET with a drive current four orders of magnitude greater than conventional TFETs, along with low subthreshold swing and threshold voltage, making it suitable for high-density, low-power integrated circuits.
Implementation Method 1
a tunneling region is modulated by a voltage applied to a gate near the tunneling region
Implementation Method 2
epitaxial deposition of SiGe drain regions
Implementation Method 3
use of high-k gate dielectrics
Data Source
AI summary
The disclosure describes a tunneling field effect transistor having an overlapping structure between the source and drain regions providing a greater tunneling area. The source or drain region may be a doped region in a semi-conductive substrate. The other source or drain region may be formed by epitaxial deposition over the doped region. The gate is formed over the epitaxial region where the doped and epitaxial regions overlap. The doped region may be formed in a fin structure with the epitaxial region and gate being formed on the top and sides of the fin.