Staggered TFT Layout for Low-Variation Display Driving
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Solution Overview
Problem
Current thin film transistors used in display devices face challenges with high current variation and limited drive performance, particularly due to shot variation in laser annealing of low-temperature polysilicon and the inability to meet narrow frame and low power consumption requirements with oxide semiconductor processes.
Innovation Solution
A display device design incorporating staggered thin film transistors with a low-temperature polysilicon channel layer in the peripheral region and an oxide semiconductor channel layer in the display region, where the oxide semiconductor transistors are formed after the polysilicon transistors to minimize parasitic capacitance and heat effects, enhancing drive performance and reducing current variation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low-temperature polysilicon thin film transistors are used with excimer laser annealing, then drive performance is improved, but current variation increases due to shot variation of the laser
Solution Approach 1:
The invention divides the transistor structure into staggered components where the channel layer is positioned separately from the source and drain electrodes. This segmentation reduces the overlap area between charged regions, thereby reducing parasitic capacitance and minimizing current variation caused by laser shot variation while maintaining high drive performance.
Solution Approach 2:
The channel layer is configured with specific local properties - it is positioned only in the region between the gate electrode and the substrate, deliberately avoiding the regions under the source and drain electrodes. This local quality configuration minimizes parasitic capacitance in critical areas while maintaining channel functionality.
2Manufacturing precision
If oxide semiconductor thin film transistors are used, then current variation decreases, but drive performance and power consumption requirements cannot be satisfied
Solution Approach 1:
The invention employs a composite material structure where the channel layer is made of oxide semiconductor material combined with a specific staggered geometric configuration. This composite approach leverages the low current variation property of oxide semiconductors while the staggered structure enhances drive performance by minimizing parasitic capacitance, satisfying both requirements simultaneously.
3Ease of manufacture
If conventional thin film transistor structures are used, then manufacturing is simpler, but parasitic capacitance increases reducing drive performance
Solution Approach 1:
The staggered configuration segments the channel layer from the source and drain electrode regions, creating a structure where the channel exists only in the space between the gate and substrate. This segmentation reduces parasitic capacitance formation while maintaining compatibility with standard thin film transistor manufacturing processes.
Solution Approach 2:
The invention utilizes spatial dimensionality by positioning the channel layer in a different spatial arrangement compared to conventional transistors. The channel is formed in the vertical space between the gate electrode and substrate rather than horizontally under the electrodes, reducing capacitive coupling while maintaining electrical functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves high drive performance and reduced current variation by minimizing parasitic capacitance and avoiding heat effects during the formation of the oxide semiconductor transistors, while also addressing the limitations of existing thin film transistor processes.
Implementation Method 1
The silicon is polycrystallized by excimer laser annealing
Implementation Method 2
The silicon is polycrystallized by excimer laser annealing
Implementation Method 3
since the first thin film transistor and the second thin film transistor are the staggered thin film transistors, parasitic capacitance becomes small
Data Source
AI summary
A plurality of thin film transistors provided in a peripheral region are first staggered thin film transistors where a first channel layer configured of low-temperature polysilicon is included, and the first channel layer is not interposed between a first source electrode and a first gate electrode, and between a first drain electrode and the first gate electrode. A plurality of thin film transistors provided in a display region are second staggered thin film transistors where a second channel layer configured of an oxide semiconductor is included, and the second channel layer is not interposed between a second source electrode and a second gate electrode, and between a second drain electrode and the second gate electrode. The first thin film transistor is located below the second thin film transistor.