Staggered Via Interconnect Structure for Multi-Thickness Semiconductor Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Forming interconnect structures for semiconductor devices with non-uniform thickness or multiple thicknesses is challenging, as deeper vias can result in unreliable connections and increased contact resistance, and separate masking and patterning processes are needed to avoid over-etching damage.
Innovation Solution
A two-step process is employed to form a staggered via structure, where a lower portion of the via is formed by patterning a first dielectric layer, and an upper portion is formed by patterning a second dielectric layer over the first, eliminating the need for additional patterning and reducing step height for improved reliability and contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single deep via is formed to connect through varying thicknesses, then electrical connection is achieved, but contact resistance increases and reliability decreases
Solution Approach 1:
The via connection path is segmented into two separate via structures at different depths. The first via connects through the first dielectric layer to the first metal line, while the second via connects through the second dielectric layer to the second metal line. This segmentation allows each via to be optimized for its specific depth and electrical requirements, reducing overall contact resistance and improving reliability.
Solution Approach 2:
The solution transitions from a single-dimensional deep via approach to a two-dimensional staggered via arrangement. By creating via structures at different depths and positions (first via at first depth, second via at second depth), the patent adds a depth dimension to the via connection strategy, allowing optimization of each via's electrical characteristics based on its specific location and required connection depth.
2Manufacturing precision
If separate masking and patterning processes are used to avoid over-etching damage, then via formation precision is improved, but manufacturing complexity increases
Solution Approach 1:
The first dielectric layer is patterned in advance to create the first via structure before forming the second dielectric layer. This preliminary patterning action defines the first via's position and dimensions early in the process, preventing over-etching damage by establishing precise etch stop planes. The second dielectric layer is then formed and patterned to create the second via, with each via's geometry predetermined by its respective dielectric layer pattern.
3Adaptability or versatility
If deeper vias are formed to reach through varying thicknesses, then interconnect coverage is improved, but contact resistance increases
Solution Approach 1:
Each via structure is given local quality optimized for its specific function. The first via is designed with dimensions and depth appropriate for connecting to the first metal line through the first dielectric layer, while the second via is designed with different dimensions and depth for connecting to the second metal line through the second dielectric layer. This local optimization ensures minimum contact resistance at each connection point while maintaining adequate interconnect coverage across varying thicknesses.
Data Source
AI summary
The present disclosure relates to a method of forming an interconnect structure that eliminates a separate deep via patterning process to simplify the fabrication process. In some embodiments, a first dielectric layer is formed over a first metal line and patterned to form a through-hole exposing a first contact region of the first metal line. A second dielectric layer is deposited and patterned to form a first via-hole connecting to the through-hole and a second via-hole exposing a second contact region of the second metal line from a layout view. A first via is formed on the first contact region extending to a first upper surface of the second dielectric layer, and a second via is formed on the second contact region extending to a second upper surface of the second dielectric layer.