Staggered Wire Bond Density for Semiconductor Packages
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Solution Overview
Problem
The challenge in miniaturizing semiconductor packages is to accommodate an increasing number of input/output (I/O) pads in a reduced area without sacrificing electrical performance or causing device functionality issues, as conventional bonding wires are limited by their thickness and pitch, leading to potential shorting or poor electrical performance.
Innovation Solution
The semiconductor package employs a combination of signal lines and power/ground lines with different thicknesses, where the thicker power/ground lines are staggered with respect to thinner signal lines, allowing for a higher density of I/O pads without compromising electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional thick bond wires are used to connect I/O pads, then device functionality is maintained, but the pitch between wires must be large preventing miniaturization and increased I/O density
Solution Approach 1:
The patent applies different wire thicknesses for different functions: thick wires (25 microns) for power/ground connections and thin wires (18 microns) for signal connections. This local differentiation allows the signal wires to be placed closer together while maintaining reliability, thus increasing I/O density without sacrificing device functionality.
2Quantity of substance
If the pitch between I/O pads is reduced to increase density, then more I/O pads can be accommodated in reduced area, but adjacent thick wires and pads become shorted destroying device functionality
Solution Approach 1:
The patent implements local quality by using thin signal wires (18 microns) in regions where high density is required, while maintaining thick power/ground wires (25 microns) where current carrying capacity is critical. This allows reduced pitch for signal pads without causing shorting, while power/ground pads maintain adequate spacing.
Solution Approach 2:
The patent staggers the arrangement of power/ground bond pads relative to signal bond pads in the vertical dimension, creating alternating rows. This dimensional rearrangement allows signal wires to be positioned between power/ground wires, effectively increasing density without reducing the pitch between power/ground connections.
3Area of stationary object
If smaller wires are used to achieve reduced pitch, then I/O density increases, but electrical performance degrades with increased resistance
Solution Approach 1:
The patent applies local quality by assigning thin wires (18 microns) specifically to signal connections where resistance is less critical, and thick wires (25 microns) to power/ground connections where low resistance is essential for maintaining electrical performance.
Solution Approach 2:
By staggering power/ground bond pads and signal bond pads in alternating rows, the patent creates a configuration where thin signal wires can be placed in the gaps between thicker power/ground wires, achieving high density while maintaining adequate electrical performance through strategic wire placement.
4Reliability
If thicker power/ground lines are used, then electrical performance improves, but the overall pitch and area required increases
Solution Approach 1:
The patent resolves this contradiction by staggering power/ground bond pads and signal bond pads in alternating rows, creating a interleaved configuration. This allows thick power/ground wires to be positioned only where needed for electrical performance, while thin signal wires occupy the spaces between them, achieving both low resistance and high density.
Data Source
AI summary
A semiconductor package provides an IC chip on at least one package substrate and including signal bond pads, ground bond pads and power bond pads. The package substrate includes signal contact pads, ground contact pads and power contact pads which are respectively coupled to signal bond pads, ground bond pads and power bond pads formed on the IC chip. The contact pads are coupled to the associated bond pads by a bonding wire. The bonding wires that connect the power and ground pads have a thickness that is greater than the thickness of the bonding wires that couple the signal pads. The various bond pads on the IC chip may be staggered to provide for enhanced compactness and integration. The package substrates may be a plurality of stacked package substrates.