Staggered Word Line DRAM Write for Image Sensor Current Control
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Solution Overview
Problem
The existing image sensor systems experience current spikes and R-C delays due to the large word length of DRAM used for frame memory, which can disrupt power voltages and impair circuit function and speed, especially when writing hyperlong words to DRAM with heavily capacitively-loaded word lines.
Innovation Solution
The image sensor employs staggered, overlapping word lines to write each group of DRAM blocks independently, reducing peak currents and R-C delays by dividing word lines into groups with staggered timing, allowing each group to write hyperlong words in parallel, and reading data from DRAM into an alignment buffer using narrower words.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hyperlong words are written to DRAM with heavily capacitively-loaded word lines, then the data transfer capability is improved, but peak currents increase causing current spikes and power voltage disruptions
Solution Approach 1:
The patent divides the DRAM array into multiple independent groups, each with its own word lines. Instead of activating all word lines simultaneously across the entire DRAM array, the system activates word lines in staggered sequences across different groups. This segmentation of the DRAM write operation into multiple independent groups reduces the peak current demand by distributing the capacitive loading across time and space.
Solution Approach 2:
The patent employs periodic, staggered activation of word lines across different DRAM groups. Rather than a single simultaneous write operation, the system uses periodic write cycles where different groups are activated at different times. This periodic action distributes the current demand over time, preventing dangerous current spikes while maintaining overall data transfer productivity.
2Productivity
If hyperlong words are written to DRAM with heavily capacitively-loaded word lines, then the data transfer capability is improved, but R-C delays increase impairing circuit function and speed
Solution Approach 1:
By segmenting the DRAM array into multiple groups with independent word line control, the patent reduces the total capacitance that must be charged simultaneously. This segmentation shortens the effective word line length and reduces RC time constants, thereby reducing R-C delays and improving circuit speed while maintaining data transfer capability.
Solution Approach 2:
The patent introduces a temporal dimension to the write operation by using staggered, periodic activation of word lines across different groups. This transforms a spatial problem (simultaneous charging of all word lines) into a temporal sequence, where groups are activated at different times. This dimensional change allows the system to maintain high data transfer capability while reducing R-C delays through distributed timing.
3Quantity of substance
If all rows of frame write into image DRAM simultaneously, then the frame memory capacity is utilized, but current spikes and power voltage disruptions occur
Solution Approach 1:
The patent divides the frame memory write operation into multiple independent groups of DRAM blocks. Each group can be written to simultaneously, but the groups themselves are activated in a staggered sequence. This segmentation allows full frame memory capacity utilization while distributing the current demand across multiple time slots, preventing current spikes and power voltage disruptions.
Solution Approach 2:
The patent merges multiple smaller write operations across different DRAM groups into a coordinated, staggered sequence. By combining the write operations of multiple groups with offset timing, the system achieves full frame memory capacity utilization while the staggered timing merges the current demands into a distributed pattern that avoids dangerous peaks.
Data Source
AI summary
An image sensor has multiple blocks each with multiple pixels; each block uses a separate analog-to-digital converter (ADC). The ADCs feed digitized images into an image DRAM, and the image DRAM feeds digitized images to an alignment buffer in turn providing images to an image processor. The ADCs feed digitized image data into the image DRAM in hyperlong words, using staggered, overlapping, word lines to write each hyperlong word. A method of imaging includes exposing a photosensor array to light, reading pixels of the array in sequence within each block of pixels, one pixel in each block simultaneously; and digitizing pixels in separate ADCs for each block. Digitized pixels are written to image DRAM as hyperlong words with one pixel from each block in parallel using staggered, overlapping, word lines. Pixels are read from the image DRAM into an alignment buffer and thence to the image processor.