Staggered Write Verify Timing for Phase Change Memory
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Solution Overview
Problem
In phase change memory and other programmable resistance memory devices, the sequential nature of verify and write operations for different resistance ranges leads to waiting times that degrade overall memory performance, as longer operations wait for shorter operations to complete, resulting in inefficient use of time during write cycles.
Innovation Solution
The method involves optimizing the timing of verify and write operations within a write cycle by adjusting their durations and start times based on the specific resistance ranges, allowing the first verify period to start after an initial time and end before a final time delay, while the first write period starts after a second time delay and ends before the final time delay, and the second verify and write periods follow similar but staggered timing, ensuring the final time delay is shorter than the sum of the first write period and the second verify period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential verify and write operations are applied to memory cells with different resistance ranges, then data accuracy is ensured, but write cycle duration increases due to waiting times
Solution Approach 1:
The patent applies preliminary action by performing verify operations on memory cells with longer verify periods before performing write operations on those same cells. This reordering allows subsequent write operations on cells with shorter verify periods to proceed without waiting, eliminating idle waiting time while ensuring data accuracy through proper verification sequencing.
Solution Approach 2:
The patent implements dynamics by dynamically adjusting the timing and ordering of verify and write operations based on the specific verify period requirements of different memory cells. Instead of a fixed sequential pattern, the system adaptively schedules operations to overlap verify and write phases across different cells, optimizing the write cycle duration while maintaining reliability.
2Reliability
If verify operations are performed before write operations for each memory cell, then data integrity is maintained, but overall memory performance degrades due to waiting
Solution Approach 1:
The patent segments the write cycle into overlapping phases by dividing memory cells into groups based on their verify period characteristics. Different segments undergo verify and write operations in staggered time windows, allowing parallel processing across segments while maintaining data integrity within each segment. This segmentation enables memory performance improvement without sacrificing reliability.
Solution Approach 2:
The patent achieves continuity of useful action by eliminating idle waiting periods through overlapping verify and write operations across different memory cells. The schedule is designed so that when one cell completes its verify operation, another cell is already in its write phase, ensuring continuous productive activity throughout the write cycle while maintaining data integrity.
Data Source
AI summary
A method for storing a data value in a memory cell is provided. The data value includes one of a first data value and a second data value respectively represented by a first and a second programmable resistance ranges. The method includes, within a write cycle, storing the first data value in the memory cell by applying a first verify operation having a first verify period and a first write operation having a first write period, or storing the second data value in the memory cell by applying a second verify operation having a second verify period longer than the first verify period and a second write operation having a second write period shorter than the first write period. The write cycle is shorter than a sum of the first write period and the second verify period.