Stair-Formed 3D NAND Mask for Etching Precision
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Solution Overview
Problem
The miniaturization of semiconductor storage devices presents challenges in creating a stair-like structure for three-dimensional stacked nonvolatile memory, where existing methods struggle to maintain uniformity and precision in etching patterns, leading to potential deviations in step positions and increased manufacturing costs.
Innovation Solution
The semiconductor storage device employs a method where resist patterns are strategically arranged and slimmed to form a stair portion with equal recession amounts between the center and corners, ensuring precise etching and reducing manufacturing costs by maintaining a linear end portion facing the scribe line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing etching methods are used to create stair-like structures, then the manufacturing process can be completed, but uniformity and precision of etching patterns deteriorate, leading to deviations in step positions
Solution Approach 1:
The patent segments the mask pattern formation into multiple steps: first forming an initial mask pattern, then forming a stair-like structure by selectively removing portions, and finally forming a refined mask pattern. This segmentation allows each step to be optimized independently, ensuring both etching uniformity and step position accuracy.
Solution Approach 2:
The patent performs preliminary actions by first forming the initial mask pattern and the stair-like structure before the actual etching process. The recess portions are pre-formed in the mask pattern, which guides the subsequent etching process to achieve precise step positions and uniform etching patterns.
2Volume of moving object
If miniaturization is pursued in three-dimensional stacked nonvolatile memory, then device density increases, but maintaining precision in stair-like structure formation becomes more difficult
Solution Approach 1:
The patent transitions from two-dimensional mask patterns to three-dimensional stair-like structures by forming recess portions at specific locations. This dimensional change allows the mask pattern to encode positional information that guides precise etching, maintaining accuracy even as device size decreases.
Solution Approach 2:
The patent changes the physical parameters of the mask pattern by forming recess portions with specific depths and positions. These parameter changes in the mask structure enable precise control over the etching process, maintaining manufacturing precision during miniaturization.
3Ease of manufacture
If conventional mask patterns are used without strategic arrangement, then manufacturing process is simpler, but etching precision and contact placement accuracy deteriorate
Solution Approach 1:
The patent introduces an intermediary structure - the stair-like mask pattern with recess portions - that mediates between the simple initial mask formation and the precise final etching results. This intermediary structure carries the positional information needed for accurate contact placement while maintaining manufacturing simplicity.
Data Source
AI summary
A semiconductor storage device according to one embodiment is the semiconductor storage device that includes: a cell array region having a plurality of memory cells; and an outer edge portion arranged at an end portion to surround the cell array region. A stacked body in which a plurality of conductive layers are stacked via a first insulating layer and which has a stair portion in which end portions of the plurality of conductive layers form a stair shape is provided inside the cell array region, the stair portion facing the outer edge portion. A center of at least one step of the stair portion has a recess directed to an inner side of the cell array region.