Stair-Shaped Raised Source and Drain Regions in Transistors
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Solution Overview
Problem
Existing semiconductor devices with raised source and drain regions (RSDs) face challenges in minimizing parasitic capacitance while reducing source and drain resistance, which complicates their fabrication and increases production costs.
Innovation Solution
The implementation of stair-shaped raised source and drain regions with extensions, formed in a single epitaxial growth step using dummy and replacement gates, along with flared spacers to guide the replacement gate material and reduce defects, facilitates the formation of stressors within the source and drain regions to enhance conductivity and minimize parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If raised source and drain regions are formed to reduce source and drain resistance, then conductivity is improved, but parasitic capacitance increases
Solution Approach 1:
The patent introduces a vertical dimension by forming raised source and drain regions that extend upward from the substrate surface. This vertical extension allows the regions to achieve lower resistance through increased cross-sectional area while the horizontal footprint remains constrained, thereby limiting parasitic capacitance. The stair-shaped configuration further optimizes this by creating multiple terraced levels that progressively reduce capacitance exposure.
Solution Approach 2:
The raised source and drain regions are segmented into multiple stair-shaped levels or terraces. This segmentation divides the continuous raised region into discrete steps, allowing each level to be optimized independently for resistance and capacitance trade-offs. The segmented structure reduces the lateral extension at each elevation, thereby minimizing parasitic capacitance while maintaining conductive pathways.
2Reliability
If complex fabrication processes are used to minimize parasitic capacitance and reduce source and drain resistance, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges multiple fabrication functions into a unified process flow. The dummy gate structure serves dual purposes: as a placeholder during fabrication and as a template for forming the stair-shaped raised regions. The replacement gate process combines spacer formation, dummy gate removal, and final gate structure creation in an integrated sequence, reducing the number of discrete process steps while achieving both low resistance and low capacitance objectives.
Solution Approach 2:
The dummy gate structure is formed preliminarily before the actual gate structure. This preliminary structure enables the subsequent formation of raised source and drain regions with precise geometric control. The dummy gate acts as a sacrificial element that guides the stair-shaped region formation, and its removal and replacement is performed as a preliminary sequence that simplifies the overall fabrication by establishing critical dimensions early in the process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, reduces parasitic capacitance, and enhances the conductivity of the channel by forming stressors in a single epitaxial growth step, thereby improving the efficiency and cost-effectiveness of transistor devices with low source and drain resistance.
Implementation Method 1
formed in a single epitaxial growth step
Implementation Method 2
provides a stress to a channel between the source region and the drain region to enhance conductivity of the channel
Data Source
AI summary
Transistor devices and methods of their fabrication are disclosed. In one method, a dummy gate structure is formed on a substrate. Bottom portions of the dummy gate structure are undercut. In addition, stair-shaped, raised source and drain regions are formed on the substrate and within at least one undercut formed by the undercutting. The dummy gate structure is removed and a replacement gate is formed on the substrate.