Stair-Stacked Memory Module in System-in-Package
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Solution Overview
Problem
The challenge in computing devices such as smartphones and tablets is the limited available space, which restricts the size reduction of packaging for systems-in-package (SiP) devices, making it difficult to efficiently stack and connect memory and processor dies while maintaining electrical connectivity and minimizing size.
Innovation Solution
The implementation of a stair-stacked memory module in a system-in-package (SiP) with vertical wire technology, where memory and processor dies are stacked in a stair-step configuration with orthogonal vertical wires and adhesives, allowing for efficient stacking and connection while minimizing space, using a matrix material for encapsulation and redistribution layers for board mounting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If memory and processor dies are stacked in a traditional flat configuration, then electrical connectivity can be maintained, but the available space is insufficient for efficient packaging in computing devices
Solution Approach 1:
The patent transitions from a traditional flat two-dimensional stacking configuration to a three-dimensional stair-step configuration. Memory dies are stacked at offset positions relative to processor dies, creating vertical layers that extend in multiple dimensions. This dimensional change allows efficient use of vertical space while maintaining electrical connectivity through orthogonal vertical wires that penetrate through the stair-step structure.
Solution Approach 2:
The stair-step configuration enables nested arrangement where multiple memory dies are stacked within the vertical space above processor dies. Each memory die is positioned at a different horizontal offset, creating a nested-like structure that maximizes space utilization. The orthogonal vertical wires are nested within the matrix material that encapsulates the entire stack, further optimizing the packaging volume.
2Volume of moving object
If stair-step stacking configuration is implemented, then space efficiency is improved, but manufacturing and assembly complexity increases
Solution Approach 1:
The patent employs preliminary action by pre-attaching memory dies to temporary carriers in the correct stair-step configuration before final assembly. This preliminary positioning ensures that when the stack is transferred to the final package, the complex offset alignment is already established, reducing the difficulty of the final assembly process. The temporary carriers hold the memory dies in their precise offset positions relative to each other.
Solution Approach 2:
The patent uses temporary carriers as intermediary elements during the assembly process. These carriers serve as mediators that hold memory dies in the correct stair-step configuration during manufacturing and testing, then are removed after final assembly. The matrix material also acts as an intermediary that encapsulates and secures the entire stair-step stack, providing structural support and electrical isolation.
3Reliability
If orthogonal vertical wires are used for connectivity, then electrical connectivity is maintained, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by creating localized bonding pads and wire attachment points at specific offset positions for each memory die in the stair-step configuration. Each vertical wire is precisely positioned to connect to its corresponding bonding pad at the appropriate horizontal offset. The matrix material provides localized support and insulation around each wire path, ensuring precise alignment and electrical isolation without requiring high precision across the entire structure.
Data Source
AI summary
A system in package includes a stair-stacked memory module that is stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die.