Stair Step Conductive Structure for High-Density Memory Connections
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Solution Overview
Problem
Conventional vertical memory arrays face challenges in efficiently providing connections to each memory cell due to the increased number of conductive connections required for high-density memory systems, making it difficult to achieve effective and efficient electrical connections in miniaturized memory devices.
Innovation Solution
A conductive structure with a stair step configuration, where each step is formed from conductive material and insulated from adjacent steps, with contacts extending through the structure to facilitate direct electrical connections to memory cells, reducing the need for complex wiring and enhancing connection efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory devices are miniaturized to increase density, then the number of memory cells per chip increases, but the number of connections required to operate each memory device increases
Solution Approach 1:
The patent transitions from planar (2D) memory array layout to three-dimensional (3D) vertical stacking architecture. Memory cells are arranged in multiple layers stacked vertically, with conductive plates and pillars extending through multiple levels. This dimensional change allows significantly more memory cells to be packed into the same chip area while providing structured pathways for electrical connections through the vertical stack.
Solution Approach 2:
The patent implements a nested structure where conductive plates are stacked vertically with insulating layers and pillars embedded within them. Each layer contains memory cells that are nested within the vertical stack, with control gates and bit lines integrated at different levels. This nested arrangement allows multiple memory cells to share common structural elements, reducing the total number of discrete connection components needed.
2Quantity of substance
If vertical memory arrays are used to increase density, then more memory cells fit in unit die area, but providing connections to each memory cell becomes difficult and inefficient
Solution Approach 1:
The patent designs conductive plates and pillars to serve multiple functions simultaneously. Conductive plates act as both control gates for memory cells in one layer and as bit lines or word lines for cells in adjacent layers. Pillars provide both structural support and electrical conduction pathways through multiple layers. This multi-functionality reduces the total number of dedicated connection structures needed, simplifying the manufacturing process despite the increased vertical complexity.
Data Source
AI summary
Conductive structures include a plurality of conductive steps and a contact extending at least partially therethrough in communication with at least one of the plurality of conductive steps and insulated from at least another one of the conductive steps. Devices may include such conductive structures. Systems may include a semiconductor device and a stair step conductive structure having a plurality of contacts extending through a step of the stair step conductive structure. Methods of forming conductive structures include forming contacts in contact holes formed through at least one conductive step of a conductive structure. Methods of forming electrical connections in stair step conductive structures include forming contacts in contact holes formed through each step of the stair step conductive structure.