Stair Step Memory Deck Structure for Precise Contact Formation
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Solution Overview
Problem
Conventional vertical memory arrays face challenges in increasing memory density without increasing the overall width of the stack structure, leading to complex and congested routing paths, and improper formation of conductive contacts due to the presence of liner materials with different etch rates.
Innovation Solution
A method of forming microelectronic devices with stair step structures, where a liner material is selectively removed from the second deck structure to improve the accuracy of electrically conductive contact placement, and dielectric material is formed within openings to facilitate proper contact formation, using materials like silicon nitride for the liner and dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If additional tiers of conductive structures are added to increase memory density, then memory density is improved, but routing path complexity and congestion increase
Solution Approach 1:
The patent transitions from planar routing to three-dimensional routing by forming stair step structures that extend vertically. Conductive contact structures are positioned at different vertical levels (steps) to access conductive structures at corresponding heights, enabling routing in the vertical dimension rather than only horizontally. This dimensional change allows additional memory tiers to be added without proportionally increasing routing complexity in the planar direction.
2Quantity of substance
If the height of the staircase structure increases to accommodate more tiers, then memory density is improved, but conductive contact formation reliability deteriorates
Solution Approach 1:
The patent modifies material parameters by selecting specific liner materials with controlled etch rates that are compatible with the etching process used to form conductive contact structures. By adjusting material composition and etch rate parameters, the liner material can be selectively removed to expose conductive structures at various heights without compromising contact formation reliability, even in tall stair step structures with many tiers.
3Ease of manufacture
If liner materials with different etch rates are used in the stack structure, then manufacturing flexibility is improved, but manufacturing precision deteriorates due to improper contact placement
Solution Approach 1:
The patent applies different liner materials with different etch rates at different vertical locations within the stack structure. Specifically, liner materials are applied to conductive structures at different heights (steps) with etch rates selected to enable selective removal during the etching process. This local differentiation of material properties allows precise control over which conductive structures are exposed at each step, ensuring accurate contact placement while maintaining manufacturing flexibility.
Data Source
AI summary
A microelectronic device comprises a first deck structure comprising alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures, a second deck structure vertically overlying the first deck structure and comprising additional tiers of the conductive structures and insulative structures, a staircase structure within the first deck structure and having steps comprising edges of the tiers, a dielectric material covering the steps of the staircase structure and extending through the first deck structure, and a liner material interposed between the steps of the staircase structure and terminating at an interdeck region between the first deck structure and the second deck structure. Related microelectronic devices, electronic systems, and methods are also described.