Stair Step Structure Error Margin Control in Semiconductor Devices
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Solution Overview
Problem
Conventional methods for forming stair step structures in semiconductor devices face challenges in achieving precise step width and position, leading to increased errors and decreased yield, especially as the number of steps increases, due to compounding margins of error in the manufacturing process.
Innovation Solution
A method involving the selective removal of photoresist and conductive/insulating structures in varying widths based on estimated error distributions, allowing for non-uniform spacing of contact structures to ensure suitable electrical contact, thereby reducing error propagation without increasing the lateral dimensions of the semiconductor device structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of steps in the stair step structure is increased to provide additional memory density, then the memory density is improved, but the margin of error for forming the steps decreases
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure before the stair step structure, which serves as a template to define the positions and dimensions of multiple steps simultaneously. This preliminary structure enables subsequent processes to form all steps with consistent precision, preventing error compounding that would occur with sequential formation of each step.
Solution Approach 2:
The mandrel structure acts as an intermediary element that mediates between the fabrication process and the final stair step structure. By forming the mandrel first and using it to guide subsequent material deposition and etching processes, the patent ensures that all steps are formed with uniform dimensions and spacing, thereby maintaining manufacturing precision even as the number of steps increases.
2Ease of manufacture
If conventional repeated trimming and etching acts are used to form each step, then the stair step structure can be formed, but errors in step width and position are compounded
Solution Approach 1:
Instead of performing repeated trimming and etching acts that compound errors, the patent uses a preliminary mandrel structure to define all step positions and dimensions in a single formation process. This eliminates the need for multiple sequential acts, thereby preventing error compounding while maintaining ease of manufacture.
Solution Approach 2:
The patent merges the formation of multiple steps into a single process by using the mandrel structure as a common reference for all steps. Rather than forming each step independently through separate trimming and etching acts, all steps are formed simultaneously or in sequence using the mandrel as a guiding template, thereby combining multiple error-prone acts into one unified process.
3Manufacturing precision
If the margin of error is reduced to less than one percent to achieve suitably sized and positioned steps, then the step precision is improved, but the yield decreases
Solution Approach 1:
By forming the mandrel structure preliminarily with high precision, the patent establishes a stable reference that enables subsequent steps to be formed with adequate margins of error. This preliminary precision work allows larger tolerances in later processes, thereby improving yield without sacrificing the required step positioning accuracy.
Solution Approach 2:
The mandrel structure provides beforehand cushioning by serving as a robust template that compensates for potential variations in subsequent processing steps. Its pre-formed, precise geometry creates a buffer that absorbs processing variations, allowing larger margins of error in later steps while still achieving the required final precision, thereby improving yield.
Data Source
AI summary
A method of forming a semiconductor device assembly comprises forming tiers comprising conductive structures and insulating structures in a stacked arrangement over a substrate. Portions of the tiers are selectively removed to form a stair step structure comprising a selected number of steps exhibiting different widths corresponding to variances in projected error associated with forming the steps. Contact structures are formed on the steps of the stair step structure. Semiconductor device structures and semiconductor devices are also described.