Stair Step Mask Layout for Smaller 3D Memory Die Footprints
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for forming stair step structures in memory devices often result in wasted area due to the formation of stair steps on all edges, which increases the effective footprint of the memory device and is inefficient.
Innovation Solution
A method using at least two masks to form stair step structures, where a first mask defines a first exposed area and a second mask defines a second exposed area that is smaller, allowing for precise removal of conductive material to create a stair step structure with controlled dimensions, thereby reducing unnecessary area formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If stair steps are formed on all edges of the memory device, then the memory device achieves a three-dimensional structure for increased capacity, but the effective footprint and die size increase unnecessarily
Solution Approach 1:
The patent applies local quality by forming stair step structures only at specific locations (circuit region edges) rather than uniformly across the entire memory array. The mask is configured to expose only the circuit region boundaries, allowing stair steps to be formed locally where interconnection coupling is needed, while leaving the memory array region without stair steps. This selective formation increases memory capacity through 3D structuring without unnecessarily increasing the overall die size.
2Ease of manufacture
If a single mask is used for stair step formation, then the process is simpler, but precise control over stair step dimensions and location is difficult to achieve
Solution Approach 1:
The patent segments the mask formation process into multiple sequential steps, where each mask step defines a specific exposed area for stair step formation. The first mask defines a first exposed area, and the second mask defines a second exposed area that is smaller and positioned to create the precise stair step dimensions. This segmentation allows independent control of each mask layer, enabling precise dimensional control of the stair steps while maintaining process feasibility through standard photolithography techniques.
3Ease of operation
If masks extend beyond the required exposed area, then mask alignment is easier, but unnecessary area is exposed leading to wasted material removal and increased die size
Solution Approach 1:
The patent configures each mask to have a specific exposed area that precisely matches the required stair step formation region. The first mask exposes only the circuit region edges, and the second mask exposes only the specific areas where additional stair step levels are needed. This precise local exposure control ensures that material removal is confined exactly to where stair steps are required, eliminating wasted material removal and preventing unnecessary die size expansion, while the mask dimensions are designed to provide sufficient alignment margins.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.