Stair Step Memory Stack Contacts for Collapse-Resistant Density
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Solution Overview
Problem
Conventional vertical memory arrays face issues with stack collapse during processing and reduced reliability due to decreased margin between conductive contact structures, making it difficult to increase memory density.
Innovation Solution
A method is introduced where first openings are formed through the dielectric material overlying the stair step structure before forming pillar structures, allowing for the creation of conductive contact structures that maintain electrical connections without pillar fall-off, thereby enhancing memory cell density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the height of stacks increases to facilitate additional memory cells, then memory density is improved, but the stack becomes prone to toppling or collapse during processing
Solution Approach 1:
The method forms openings through the dielectric material overlying the stair step structure before forming the pillar structures. This preliminary action allows conductive contact structures to be positioned in predetermined locations, providing early structural support and electrical connections that prevent stack collapse during subsequent processing steps
Solution Approach 2:
The conductive contact structures serve as intermediary elements that provide both structural support and electrical connections. By positioning these contact structures in openings formed before pillar formation, the invention creates a stable framework that mediates between the need for high memory density and the requirement for stack stability
2Quantity of substance
If the density of vertical memory strings increases, then memory density is improved, but the margin between conductive contact structures and other structures decreases
Solution Approach 1:
By forming openings through the dielectric material before creating pillar structures, the method establishes precise locations for conductive contact structures in advance. This preliminary positioning ensures adequate margins between contact structures and other components, even as vertical memory string density increases
Solution Approach 2:
The stair step structure is divided into multiple tiers with individual steps, allowing conductive contact structures to be positioned at specific locations on different tiers. This segmentation enables independent optimization of contact structure placement, maintaining necessary margins while increasing overall memory density
3Quantity of substance
If replacement gate processing is performed on tall stacks, then memory density is improved, but tier collapse occurs during or after removal of portions to be replaced
Solution Approach 1:
The conductive contact structures are formed in predetermined locations before the replacement gate processing and tier removal steps. This preliminary formation of stable electrical connections ensures that even if tier collapse occurs during processing, the fundamental reliability of the vertical memory strings is preserved
Solution Approach 2:
By establishing conductive contact structures in advance, the invention creates a cushioning effect that protects against reliability degradation. These pre-formed structures provide a stable foundation that compensates for potential damage or collapse that may occur during subsequent replacement gate processing
Data Source
AI summary
A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, a stair step structure within the stack structure and having steps comprising lateral edges of the tiers, pillar structures extending through the stack structure and the stair step structure and in contact with a source tier vertically underlying the stack structure, and conductive contact structures in contact with the steps of the staircase structure, the conductive contact structures individually comprising a first portion and a second portion vertically overlying the first portion, the second portion vertically above the pillar structures and having a greater lateral dimension than the first portion. Related microelectronic devices, memory devices, and electronic systems are also described.


